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. 2020 Jul 16;11:3566. doi: 10.1038/s41467-020-17297-z

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© The Author(s) 2020

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 4 — a Electrical schematic and b optical image of an inverter. c Output voltage (left axis) and voltage gain (right axis) of the inverter gate as a function of the input voltage. d Electrical schematic and e optical image of a NAND gate. f Output voltage of the NAND gate as a function of the input states (V_IN1, V_IN2). Voltage bias is 5 V for both the inverter and the NAND gate. g Electrical schematic and h optical image of a current mirror. i Output current of the current mirror as a function of the output voltage for two different values of the reference current. Legend: V_DD, supply voltage; GDN, ground reference; V_IN and V_OUT, input and output voltage; M, inkjet-printed transistor. R, inkjet-printed graphene resistor. The scale bars in b, e, h correspond to 250 μm.