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. 2020 Aug 27;11:4309. doi: 10.1038/s41467-020-18006-6

Fig. 4. Wafer-scale uniformity and the CMOS inverter integration with n-channel IGZO TFTs.

Fig. 4

a Photograph of CuI:Zn5mol% TFT array on a 4-inch Si/SiO2 (100 nm) wafer substrate (dot line means measurement area). b, c Statistical results of μsat and Ion/Ioff obtained from 96 TFTs across the array. df Voltage transfer, gain, current characteristics, and noise margin (NM) extraction of the complementary inverter based on n-type IGZO/SiO2 and p-type CuI:Zn/SiO2 TFTs.