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. 2020 Sep 14;11:4595. doi: 10.1038/s41467-020-17850-w

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© The Author(s) 2020

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 5 — a Schematic illustration of AND and OR logic gates implemented using proposed synaptic array with size of 2 × 3. b Simplified diagram of NN for AND and OR logic gates. c Truth table of AND and OR logic gates. d Real-time training and classification of AND and OR gates using implemented synaptic array. e Schematic illustration of two-layer perceptron-based ANN with size of 400 × 200 × 10. f Recognition rate as a function of number of training epochs for 10 synaptic devices; the maximum, average, and minimum recognition rates are indicated in blue, purple, and red, respectively. g Maximum (blue) and final (black) recognition rates of 10 synaptic devices.