Table 9.

FPGA and ASIC implementation results, where SM and AE-P denote Security-module and AE-protocol respectively.

Encryption scheme	FPGA		ASIC
	LUT	FlipFlop	Area ($\mathrm{\mu }$m${}^2$)	Delay (ns)	Power (mW)	GE (SM)	GE (AE-P)
ACORN	731	476	23 321.49	1.42	1.003	3338	6743
ASCON	1540	980	41 962.73	0.59	1.167	12 157	15 565
AEGIS-128	5582	1970	110 996.52	1.71	7.396	38 934	42 342
OCB	4124	1699	245 625.71	0.62	5.869	71 966	75 374
COLM	7535	2771	276 981.16	0.61	4.690	107 810	111 218