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. 2020 Sep 14;91(9):093702. doi: 10.1063/5.0015512

FIG. 5.

FIG. 5.

Example array design methodology. (a) Basic schematic of the layered array geometry. (b) Example Delaunay triangulation used for mesh design and Voronoi partition used for fiber void design for a single Dual-Slope (DS) set. (c) Basic schematic of parting line locations and fixture clamping methodology used to design the array mold.