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. 2020 Sep 28;23(10):101614. doi: 10.1016/j.isci.2020.101614

Figure 4.

Figure 4

A Proposed 3D SOT-MRAM

Schematic of proposed single two-terminal SOT-MTJ cell (A) and the corresponding integrated 3D SOT-MRAM architecture (B). Writing and reading currents can be addressed to a specific MTJ cell by controlling the transistor switches and selectors. FL, free layer; RL, reference layer; SEL, selector; TE, top electrode.