Table 1.
Memristive (Resistive Memory) Devices Based on 2D Materials
| Working Principle | Active Layer | Electrode | Device | Growth/Fabrication Method | Power Consumption/Switching Voltage | Ref. |
|---|---|---|---|---|---|---|
| Phase change memristor | ML-MoS2 | Au (top) | Phase change memristor | Mechanical exfoliation | 6 V | (Zhu et al., 2019) |
| 2H (semiconductor) ↔ 1T′ (metal) | ||||||
| Phase change memristor | ML-MoTe2 | Ti/Ni (top), Ti/Au (bottom) | Resistive random access memory | Mechanical exfoliation | 2.3 V | (Zhang et al., 2019) |
| 2H (semiconductor) ↔ 2Hd (transient state) | ||||||
| Conductive filament | ML-MoS2 | Ag/Au (top), Ti/Au (bottom) | Artificial neuron | CVD | 0.35–0.4 V | (Dev et al., 2020) |
| Grain boundary-mediated transport | ML-MoS2/1L-graphene | Ni (top), graphene (bottom) | Artificial neuron | CVD/Wet transfer | 2.8–2.9 V | (Kalita et al., 2019) |
| Conductive filament | BL-MoS2 | Cu (top), Au (bottom) | Synapse | MOCVD/Layer-by-layer stack | 0.1–0.2 V | (Xu et al., 2019) |
| Conductive filament | ML-h-BN | Ag (top), Cu (bottom) | Resistive memory | CVD/Wet transfer | 0.72 V | (Qian et al., 2016) |
| Conductive filament/interface-mediated switching | ML-MoS2/1L-graphene | Ni/Au (top), graphene (bottom) | Synapse | CVD/Wet transfer | 1.5 V | (Krishnaprasad et al., 2019) |
| Conductive filament | ML-h-BN-PVA composite | Ag (top), ITO (bottom) | Flexible resistive memory | Solution/liquid exfoliation | 0.78 V | (Siddiqui et al., 2017) |
| Vacancy migration | ML-WS2 | Pd (top), Pt (bottom) | Synapse | Solution | 0.56–0.67 V | (Yan et al., 2019b) |
| Space-charge-limited current | ML-MoS2-PVA | Ag (top), Ag (bottom) | Flexible resistive memory | Solution/liquid exfoliation | 3 V | (Rehman et al., 2016) |
| Space-charge-limited current | ML-MoS2-PVA | Al (top), rGO (bottom) | Flexible resistive memory | Solution/liquid exfoliation | 3.5 V | (Liu et al., 2012) |
| Atom switch | 1L- or BL-graphene | Au | Atomic-scale switches (lateral) | Electrical breakdown of graphene sheets/mechanical cleavage | – | (Standley et al., 2008) |
| Atom switch | ML-graphene | Au | Atom switches (lateral) | Feedback-controlled electro-burning/mechanical exfoliation | 0.3 V | (Sarwat et al., 2017) |
| Charge trapping/detrapping | WS2/ZnO | Ag (top), Al (bottom) | Memristors | RF sputtering | 0.8–1.6 V | (Kumar et al., 2019) |
| Charge trapping/detrapping | 1L-MoS2/h-BN/1L-graphene | Cr/Au (top) | Two-terminal floating-gate memory | CVD/mechanical exfoliation | – | (Vu et al., 2016) |
| Charge trapping/detrapping | ML-WSe2/WCL/h-BN | Ti/Au (control), Pt/Au (synaptic) | Optic-neural synaptic device | O2 plasma treatment/residue-free transfer | 66 fJ at 0.3 V pulse | (Seo et al., 2018) |
| Charge trapping/detrapping | ML-MoS2/h-BN/graphene/h-BN | Cr/Au (top), Si (bottom gate) | Human memory system programming: sensory memory, short-/long-term memory | Mechanical exfoliation/PVA transfer | 64 pJ | (Chen et al., 2019a) |
| Charge trapping/detrapping | Au/h-BN/ML-MoS2/h-BN graphene or ML-MoS2/h-BN/ML-MoS2/h-BN | Cr/Au (top), p++-Si (bottom gate) | Multilevel optical memory | Mechanical exfoliation/PDMS stamping | – | (Kim et al., 2019c) |
| Charge trapping/detrapping | ML-MoS2/h-BN/graphene | Cr/Au (top), p++-Si (bottom gate) | Synaptic transistors | Mechanical exfoliation/dry transfer | 5 fJ | (Paul et al., 2019) |
| Charge trapping/detrapping | ML-MoS2/PTCDA | Au (top), n++-Si (bottom) | MoS2/PTCDA heterojunction synapse | Mechanical exfoliation | 10 pJ | (Wang et al., 2019b) |
| Charge trapping/detrapping | ML-MoS2/h-BN/h-BN/Au substrate | Au or Al (top), Au, Al, Pd, or highly doped Si (bottom gate) | Flash memory devices | Mechanical exfoliation | – | (Yi et al., 2018) |
| Gate-tunable memristor | 1L-MoS2 | Ti/Au (top S, D, gate) | Memtransistor | CVD | – | (Wang et al., 2019a) |
| Gate-tunable memristor | 1L-MoS2 | Au (top), Si (bottom gate) | Memtransistor | CVD | 3.5–8.3 V | (Sangwan et al., 2015) |
| Gate-tunable memristor | ML-GaSe | Ag (side), Si (bottom gate) | Memtransistor | Mechanical exfoliation | 0.8–1.8 V | (Yang et al., 2019b) |
| Gate-tunable memristor | ML-MoS2 | Ti/Au (top), Si (bottom gate) | Memtransistor | Mechanical exfoliation | Dual gate: Light (0.63 mW)/∼3 V | (Yin et al., 2019b) |
| Gate-tunable memristor/defect engineering | 1L-MoS2 | Ti/Au (top), doped Si (bottom gate) | Memtransistor | CVD | Threshold voltage: 20 V (HRS), 10 V (LRS) | (Sangwan et al., 2018) |
| Gate-tunable memristor/defect engineering | 1L-MoS2 | Ti/Au (top), doped Si (bottom gate) | Memtransistor | CVD/focused He+ beam | 16 nW (standby), 0.64 μW (operation) | (Jadwiszczak et al., 2019) |
| Gate-tunable memristor/defect engineering | 1L-MoS2 | Ti/Au (top), n++-Si (bottom gate) | Memtransistor | CVD/focused electron beam | – | (Xie et al., 2017) |
| Defect engineering | ML-MoS2 | Ni (top), p++-Si (bottom gate) | Synaptic transistors | Mechanical exfoliation | – | (Arnold et al., 2017) |
| Defect engineering | 1L-MoS2 | - (top), n++-Si (bottom gate) | Non-volatile memory | CVD | 5-9 V | (He et al., 2016) |
| Defect engineering | ML-MoS2 | Graphene or Au (top and bottom) | Memristors | Mechanical exfoliation/PVA transfer | – | (Wang et al., 2018) |
| Defect engineering | ML-WSe2, ML-MoS2 | Ti/Au (top), p+-Si (bottom gate) | Synaptic transistors (FETs) | Mechanical exfoliation | 0.03–3 μW | (Chen et al., 2017b) |
1L, one layer; ML, multi-layer; BL, bilayer; PTCDA, perylene-3,4,9,10-tetracarboxylic dianhydride; MOCVD, metal organic chemical vapor deposition; PDMS, polydimethylsiloxane; PVA, polyvinyl alcohol; HRS, high-resistance state; LRS, low-resistance state; RF, radio frequency