Fig. 1. Compensated control voltages within a two-dimensional silicon quantum-dot array.

a Foundry-fabricated undoped silicon channel connected to reservoirs (dark gray), with four gate electrodes (light gray). This SEM image shows a device from a different fabrication run without backend¹⁶. b Device schematic for the example of a few-electron double dot underneath gates G₁ and G₄, induced by appropriate control voltages V_1–4. Each of the three qubit dots (dot 1 indicated in red) capacitively couples to the sensor dot (black), which can be monitored using RF reflectometry off an inductor (L) wirebonded to G₄. c, d Charge stability diagram of the double quantum dot in b, acquired at fixed source–drain bias V = −3 mV. Source–drain current I and demodulated reflectometry voltage V_H measured simultaneously as a function of V₁ and V₄. The dotted white line defines a compensated voltage $V_{\mathrm{1}}^{\mathrm{c}}$ that controls the chemical potential of dot 1 without affecting the chemical potential of dot 4. Control voltages $V_{\mathrm{1,2,3}}^{\mathrm{c}}$ for other dot configurations are established analogously.