Figure 2.

Transfer process and characterization of an exfoliated large-area MoS₂ flake transistor

(A) Schematic illustration of the gold-mediated exfoliation process.

(B) Optical image of an exfoliated MoS₂ flake with a lateral size of ~200 × 100 μm on a SiO₂/Si substrate.

(C) Room-temperature Raman spectrum of MoS₂ showing the A_1g mode at 408 cm⁻¹ and the E¹_2g mode at 385 cm⁻¹.

(D) High-resolution TEM image of the atomic layer of MoS₂. Inset is the zoom-in view exhibiting a lattice d100 of 0.27 nm.

(E) Histogram comparing flake area size between traditional mechanical exfoliation (in red) and the gold-assisted exfoliation method (in blue).

(F) 3D schematics of the back-gated FET device on the SiO₂/Si substrate.

(G) Optical image of the MoS₂ FET device from the top. Different channel lengths were fabricated for optimization of the design.

(H) Output curve (source-drain current I_DS versus source-drain voltage V_DS) with the back-gate voltage V_G sweep from 0 to 60 V.

(I) Transfer curve (I_DS as a function of V_G) with V_DS = 5 V, shows n-type behavior with an on/off ratio of 10⁷.