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. 2021 Jan 29;12:693. doi: 10.1038/s41467-020-20732-w

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© The Author(s) 2021

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 3 — A total of 230 MoS₂ FETs and 160 WS₂ FETs were fabricated using 23 and 16 TLM structures with channel lengths ranging from L_CH = 100 nm to L_CH = 5 μm for a MoS₂ and b WS₂, respectively, to analyze the device-to-device variation and impact of scaling on the device performance. The corresponding transfer characteristics, i.e., I_DS versus V_GS, for V_DS of 1 V are shown in the logarithmic scale.