Table 1.

Benchmarking device-to-device variation in threshold voltage.

	${\mathbf{\sigma }}_{V_{\mathrm{t}}}\left(\mathrm{V}\right)$	Gate dielectric	$S{\mathbf{\sigma }}_{V_{\mathrm{t}}}\left(\mathrm{V}\right)$ at SEOT = 0.9 nm	Channel dimensions (µm)
25—MoS2	1.05	30 nm SiO2	33 × 10−3	W = 11.6, LCH = 4–8.6
26—MoS2 1 continuous layer	0.25	30 nm HfO2	45 × 10−3	W = –, LCH = 30
26—MoS2 1 layer + ML	0.1	30 nm HfO2	19 × 10−3	W =  –, LCH = 30
12—MoS2	0.17	30 nm Al2O3	11 × 10−3	W = 30, LCH = 4
7—MoS2	44 × 10−3	4 nm HfO2	20 × 10−3	W = 1, LCH = 0.1
Our work-MoS2, WS2	0.8	50 nm Al2O3	33 × 10−3	W = 5, LCH = 0.1, 0.2, 0.3, 0.4, 0.5, 1, 2, 3, 4, 5
33—UTB SOI	24.5 × 10−3	EOT = 1.65 nm	13 × 10−3	W = 0.060, LCH = 0.025
32—FinFET	10 × 10−3	EOT = 0.8 nm	11 × 10−3	W = 0.0075, LCH = 0.034