Table 2. Component-wise performance comparison of SC CNN.
| SC CNN/BNN components | Author | Platform/ software | Relative accuracy (%) | Area/gate count (%) | Power/Energy saving (%) | Relative to |
|---|---|---|---|---|---|---|
| Integra SC | Ardakani et al. (2017) | FPGA & ASIC | +0.03 | −33.9 | 21.3 | Binary computing |
| ESL | Canals et al. (2016) | FPGA | −2.23 | – | – | Binary computing |
| APC + Btanh | Kim, Lee & Choi (2016a), Kim, Lee & Choi (2016b) and Kim et al. (2016) | Synopsys Design Compiler | −0.18; −1.71 (EDT) | −50.0 | 70.0; 76.2 (EDT) | Binary computing |
| APC with inverse adder | Li et al. (2018a) | Synopsys Design Compiler | – | −50.0 | 10.0 | Normal APC |
| SC MaxPooling | Ren et al. (2017) | Synopsys Design Compiler | −0.20 | −92.7 | 98.3 | GPU computing |
| SC ReLU activation | Li et al. (2018a) | Synopsys Design Compiler | −0.88 | −95.3 | 99.1 | GPU computing |
| SC normalisation | Li et al. (2017b) | Synopsys Design Compiler | −0.02 | −83.8 | 88.9 | Binary computing |
| SC MAC | Sim & Lee (2017) | Synopsys Design Compiler | −1 | −93.9 | −89.4 | Binary computing ASICa |
| SC DMAC | Hojabr et al. (2019) | Synopsys Design Compiler | – | −73.5 | 292 | AlexNet |
| 147 | InceptionV3 | |||||
| 370 | VGG16 | |||||
| 12 | MobileNet | |||||
| SC Sigmoid activation | Li et al. (2017a) | FreePDK | −0.01 | −96.8 | 96.7 | Binary computing |
| SC Quantization | Li et al. (2018b) | FreePDK | −0.79 | −98.6 | 99.1 | Binary computing |
| – | −45.7 | 77.9 | Unipolar SC | |||
| – | −60.3 | 85.8 | Bipolar SC | |||
| SC BNN | Hirtzlin et al. (2019) | Cadence First Encounter | −1.40 | −62.0 | 240 | Binary BNN |
Notes.
a
Binary computing ASIC apply to the CNN model comparison.