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. 2021 Mar 8;7:e404. doi: 10.7717/peerj-cs.404

Table 2. Memory of CUDA-capable GPU (NVIDIA, 2020a).

Memory Location on/off chip Access Scope Lifetime
Register On R ∕W 1 thread Thread
Local Off R ∕W 1 thread Thread
Shared On R ∕W All threads in block Block
Global Off R ∕W All threads +host Host allocation
Constant Off R All threads +host Host allocation
Texture Off R All threads +host Host allocation