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. Author manuscript; available in PMC: 2021 Sep 1.
Published in final edited form as: IEEE J Solid-State Circuits. 2020 Jul 9;55(9):2567–2582. doi: 10.1109/jssc.2020.3005816

Fig. 3.

Fig. 3.

(a) Active pixel circuit schematic. The switches (transmission gates) are controlled by the transparent latch memory to configure the pixel for experiments. C1 = 3.5 pF; C2 has the options of adding any of ∼5 fF, ∼20 fF, and ∼100 fF. (b) Active pixel circuit layout. Metal-insulator-metal capacitors are identified on the topmost metal layers. (c) Transistor-level schematics of various pixel components, in particular, op-amp (left), transparent latch (middle), and output multiplexer (right); the schematic of the current injector is shown in detail in Fig. 7.