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. Author manuscript; available in PMC: 2021 Sep 1.
Published in final edited form as: IEEE J Solid-State Circuits. 2020 Jul 9;55(9):2567–2582. doi: 10.1109/jssc.2020.3005816

Fig. 6.

Fig. 6.

(a) Timing diagram for IOUT, IOUT,R IOUT,C, and V1, VSC, VOUT. (b) VOUT(t) for the RLCL load (cyan, solid) in juxtaposition with VOUT(t) for a CL-only load (blue, solid). The response of the RLCL load to an ideal step current is overlaid (red, dashed) for comparison.