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. Author manuscript; available in PMC: 2021 Sep 1.
Published in final edited form as: IEEE J Solid-State Circuits. 2020 Jul 9;55(9):2567–2582. doi: 10.1109/jssc.2020.3005816

Fig. 8.

Fig. 8.

(a, left) pCC clocking scheme to synchronize the switched-capacitor current injector’s fsc to the multiplexer sampling at fs. Black indicates fsc high, white indicates fss low. The clock sequence is repeated after 128/fs . (right) ∆VOUT is increased due to the scheme. (b) Simulated VOUT traces for positive current injection for three different magnitudes and their steady state VOUT(t) ripple voltage.