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. 2021 Apr 16;21(8):2822. doi: 10.3390/s21082822

Figure 7.

Figure 7

Optimisation provided the same value for trace width and spacing, for PCB planar coils on the centimetres scale. To minimise the parasitic capacitance of the winding, it is convenient to shift the footprints of subsequent layers, so that the traces do not overlap.