Table 11.

Some DNN Optimization Schemes.

Ref.	Embedded Architecture	Model	Optimization Techniques	Application
[20]	FPGA(Zedboard development board)	DNN(Mnist)	Data Access Optimization, Time-sharing computation	Image Recognition
[22]	Xilinx XC7Z2020 FPGA	DNN(Mnist)	Tiling and reuse techniques, FIFO Buffering, Pipelining	Image Recognition
[51]	Xilinx Zynq ZC706 FPGA	CNN(VGG16)	Simple Vector Decomposition, Quantization, Tiling, and reuse, Buffer Design	Image Classification
[112]	Altera Stratix-V FPGA (DE5-Net, P395-D8)	CNN(AlexNet, VGG)	Number Precision, Throughput optimization through design space exploration.	Image classification
[25]	Virtex7 VX485T FPGA	CNN	Loop unrolling, Pipelining, Tiling, and data reuse	Image classification
[111]	Xilinx XC6VLX240T FPGA	CNN(LeNet-5), DNN(AlexNet)	Acceleration of Activation function, Pipelining	Image recognition and Classification.
[27]	Xilinx Vertex-7 FPGA	CNN(AlexNet-5)	Network Pruning, Quantization, hardware acceleration	Computer Vision
[125]	Intel Core i7 CPU	CNN(LeNet-5)	Adaptive Quantization	Image classification
[23]	Xilinx Zynq ZC7020 FPGA	RNN(LSTM)	Data Access Optimization, reduced precision, Buffer design	Speech Recognition