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. 2021 Jul 28;11:15307. doi: 10.1038/s41598-021-94691-7

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© The Author(s) 2021, corrected publication 2021

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(a) Example of 6 8-bit inputs FLP adder tree. (b) Architecture of a FLP adder. (c) Architecture of the optimized FLP adder used in the first level of the tree.