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. Author manuscript; available in PMC: 2022 Jul 1.
Published in final edited form as: IEEE J Solid-State Circuits. 2021 Feb 9;56(7):2142–2157. doi: 10.1109/jssc.2021.3056040

Fig. 14.

Fig. 14.

(a) Measurement setup for testing the performance of the artifact canceler. (b) Off-chip voltage summation circuitry. (c) Timing diagram of the successive operation cycles and phases.