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. Author manuscript; available in PMC: 2022 Jul 1.
Published in final edited form as: IEEE J Solid-State Circuits. 2021 Feb 9;56(7):2142–2157. doi: 10.1109/jssc.2021.3056040

Fig. 5.

Fig. 5.

(a) Simplified block diagram of the front-end configuration. (b) Differential-mode artifact cancellation at the LNA input and common-mode limitation (VCMST: body bias voltage).