TABLE I.

Performance Summary and Comparison with the State-of-the-art Bidirectional Neural Interfaces

	This work	[28] VLSI’ 17	[39] JSSC’ 20	[42] SSCL’ 18	[43] JSSC’ 16	[32] TBCAS’ 18	[17] VLSI’ 16	[38] VLSI’ 17	[24] JSSC” 6	[15] JSSC’ 18
Technology (nm)	180	180 HV	130	65	180	40/HV 180a	180	65	180	130
Supply voltage (V)	1, 3	1, 3∼12	0.6, 1.2, 3.3	1	-	0.6, 1.2, 1.8, ±5	0.8, 3.3	0.5, 2.5	1.8, 2, 3∼12	1.2, 3.3
IRNb (μVrms)	6.2c/11d,e	1.6	1.6	7.5c/8.2d	3.05	2.2	5.9f	2.78	2.09	12.0
Signal BW (Hz)	200 g -9k	DC-500	1–500	10–8.3k	1–2k	1–250	17–1.65k	1–1k	0.59–117	0.5–10k
Voltage gain (dB)	27.6–50.0	NA	NA	45–65	40–60	NA	42	NA	50–70	6–69.5
ADC res./ENOB(b)	10/8.6	15/10.2	12/11.3	10/-	10/-	NA/12.8	8/-	14/-	10/7.8i	10/-
THDj	0.9% 2mVpp,in 1kHz 50dB	0.7% 0–1Vpp,in 60Hz	-	0.4% 1.2mVpp,in 1kHz 65dB	-	0.009k% 0–1Vpp,in 203Hz	-	-	0.4i% 8.9mVpp,in 97Hz 50dB	0.89% 20mVpp,in 10kHz 54dB
AFE power/Ch(μW)	2.5	NA	NA	1.8	0.24	NA	0.8	2.98i	3.75	25.2
ADC power/Ch(μW)	0.38	8.0	1.7	-	0.09	8.2	-	-	-	0.88
Canc. power/Ch(μW)	1.42	NA	NA	0.9	-	NA	NA	-	NA	NA
Rec. area/Ch (mm2)	0.66	-	0.023	0.18	0.17	0.12	0.04	0.15	0.56	0.1h
# Rec front-ends / Stimulation cores	8 / 2	64 / 4	32 / 32	64 / 2	8 / 4	32 / 8	16 / 1	1	16 / 16	1024 / 64
# Artifact cancelers	8	0	0	8	8	4	0	1	0	0
Artifact cancellation method	FE filter	NA	NA	FE filter	FE filter	BE filter	NA	FE template subtraction	-	-
# Filter taps, type and learning algorithm	2, IIR, sign-sign LMS	NA	NA	32, FIR, sign-sign LMS	8, FIR, sign-sign LMS	16, FIR, normalized LMS	NA	NA	NA	NA
Max # uncorrelated stimulation artifacts mitigated by each canceler	2	NA	NA	1	1	1	NA	1	NA	NA
Die size (mm2)	11.76	11.52	1.0h,l	5.14	1.74l	9.88/16.43a	1.1l	-	25.0	192m

AFE: LNA+PGA, FE: front-end, BE: back-end

NA: Not applicable

-: Not reported

^aSeparate neural recording and stimulation chips in different technologies were fabricated.

^bIntegrated input referred noise measured for the reported bandwidth.

^cStandalone AFE w/o the front-end CDAC.

^dw/ the front-end CDAC.

^eAFE (max gain setting)+ADC quantization noise.

^fMeasured for 10Hz-10kHz.

^gThe high-pass corner was limited because the pseudo-resistors in the amplifier had to be shorted to prevent any disruption in the biasing due to the substrate DC leakage currents.

^hEstimated.

ⁱAFE+ADC.

^jTHD measured for the given single-tone input amplitude, frequency and AFE gain.

^kReported HD3, the design uses a nonlinearity correction block.

^lActive area (excluding pads).

^mIncludes 16k electrode sites and active pixels.