Listing 3. TCL script that automates HLS tools on the Cloud/Host server.

# Create project, add IP template, and~choose the SoC create_project DNN add_files IP_template_cpp set_top layer_fpga set_part {ZYNQ_7020} create_clock -period 10 -name~default   # Set the appropriate optimization directives according to user configurations set_directive_allocation -limit 2 -type operation DSP_fmul set_directive_allocation -limit 2 -type operation DSP_fdiv set_directive_allocation -limit 2 -type operation DSP_fadd set_directive_array_partition -factor 2 "layer_1" local_memory set_directive_unroll "layer_1/loop1" set_directive_pipeline "layer_1/loop3" set_directive_unroll "layer_1/loop1" ...   # Interfacing the IP layer with the appropriate AXI protocol for each I/O port set_directive_interface  s_axilite "layer_1" set_directive_interface  s_axilite "layer_1" set_directive_interface -mode m_axi -depth size_layer_1 weight_bias set_directive_interface -mode m_axi -depth size_layer_1 layer_weights set_directive_interface -mode m_axi -depth size_layer_1 input set_directive_interface -mode axis layer_1 output ...   # Launch synthesis and encapsulate the IP csynth_design export_design -rtl vhdl -format~ip_package   # Target the board and specify the name of the dynamic library PLATFORM = PYNQ-z1 LIBRARY = lib\_DNN.so   # Create an object file for each layer layer_1_fpga.o: layer_1 layer_2_fpga.o: layer_2 layer_3_fpga.o: layer_3 ...   # Create C/C++ shared library for the DNN FPGA architecture {LIBRARY}: layer_1_fpga.o layer_2_fpga.o layer_3_fpga.o~-shared   # Generate the bitstream file of the FPGA create {LIBRARY}.bit