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Measured computing-in-memory waveforms of skewed 3T3R SRAM cell
(A and D) Circuit diagram of 3T3R computing-in-memory SRAM cell with NAND and NOR operations, respectively.
(B and E) Waveform test of NAND and NOR computing-in-memory operation.
(C and F) The output results of NAND and NOR computing-in-memory operation at different input conditions and storage states.
