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. 2021 Nov 19;3(12):5240–5247. doi: 10.1021/acsaelm.1c00729

Figure 2.

Figure 2

(a) Schematic representation of the nanowire prior to gate deposition, where the thickness of the HSQ spacer defines the position of the gate. (b) Transfer characteristics (linear scale) at VDS = 500 mV representing the on-state for varied gate position LHSQ. (c) Transfer characteristics (log scale) at VDS = 50 mV representing the off-state for varied gate position LHSQ.