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. Author manuscript; available in PMC: 2022 Dec 9.
Published in final edited form as: IEEE Trans Biomed Circuits Syst. 2021 Dec 9;15(5):877–897. doi: 10.1109/TBCAS.2021.3112756

Fig. 11:

Fig. 11:

The number of extracted features in DVTE for different regularization coefficients. With greater C, the cost-aware model tends to use hardware-friendly features (e.g., LLN, Var). Features with longer windows (δ, θ, α) are also penalized in the cost-aware model. The power cost and latency for each C are shown in the legend, while the X-axis shows individual feature costs. For C = 0.01, we achieved an average power cost of 268nW and latency of 0.52s.