Skip to main content
. Author manuscript; available in PMC: 2022 Dec 9.
Published in final edited form as: IEEE Trans Biomed Circuits Syst. 2021 Dec 9;15(5):877–897. doi: 10.1109/TBCAS.2021.3112756

Fig. 16:

Fig. 16:

The power-latency trade-off with parallel node evaluation. With more nodes evaluated in parallel, latency is reduced at the cost of increased power consumption. Experiments were conducted with ResOT on epilepsy task.