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. 2022 Jan 29;13(2):228. doi: 10.3390/mi13020228

Figure 23.

Figure 23

(a) The inverted topography of the 16 nanoscale hole array with 55 nm periodicity. (b) An image of the channel barrier and insulated gate. (c) The process of a single-electron transistor fabrication using the mixture of the mechanical approach based on AFM fabrication, dry etching, and lift off. Reprinted with permission from Ref. [134]. Copyright 2022 AIP Publishing.