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. 2022 Mar 5;14:71. doi: 10.1007/s40820-022-00816-6

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© The Author(s) 2022

Open AccessThis article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 6 — Memristor devices mediated by charge trapping and de-trapping. a The van der Waals heterostructure device composed of MoS₂/hBN/graphene/hBN layers. b Illustration of volatile characteristics in top gate operation. c Illustration of nonvolatile characteristics in back gate operation. d Memory type transition from STM to LTM.

Reproduced with permission from Ref. [116]. Copyright 2019, Advanced Science. (Color figure online) e Schematic structure of the Ag/ZnO/WS₂/Al memristor. f PPF decays as a function of pulse interval (Δt) at different pulse amplitude and different pulse widths. g Experimental results for STDP. h The STM to LTM transition and the conductance variation by increasing input pulse voltage from + 0.7 to + 1.0 V. i Images of the letters “C” and “T” memorized in STM and LTM mode respectively. j The measured current history of the 3 × 3 arrays from right after to 30 s after the written processes. Reproduced with permission from Ref. [149]. Copyright 2019, Advanced Electronic Materials. (Color figure online)