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. 2021 Aug 17;15(9):14813–14821. doi: 10.1021/acsnano.1c04867

Figure 2.

Figure 2

CuPc self-assembled (SA) layer on MAPbI3. (a) Overview STM image showing a CuPc SA layer on top of MAPbI3. (b) Zoom-in STM image of a CuPc SA layer showing the bright-dark alternating rows of protrusions. Colored lines show the directions of interest, with correspondingly colored brackets denoting the distance of one period. Angles relative to the b-direction (blue line) along the SA layer are noted. Inset: High isosurface density value (“high resolution”) DFT simulated STM image of the (100) surface of α-CuPc. (c) Schematic denoting the CuPc polymorph stacking angle convention used here. (d) Crystal structure showing the (100) surface of α-CuPc. (e) Low isosurface density value (“low-resolution”) DFT simulated STM image of the (100) surface of α-CuPc. Image sizes: (a) 16.4 × 29.7 nm2 and (b) 4.5 × 4.5 nm2. Imaging parameters: (a) sample bias voltage = −2.7 V, tunneling current = 100 pA; (b) sample bias voltage = −2.6 V, tunneling current = 150 pA.