Figure 28.

(a) Source-drain voltage V_sd versus a gate voltage V_g statistics of 36 nanowire parallel array FET devices. Each device consists of 500–1000 nanowires. Off-current versus on-current per mm electrode width for V_sd = 0.5 V. The on/off ratio is shown for devices with four different inter-electrode spacing but the same silicidation process (green/stars 2.5 µm; red/triangles 3.5 µm; purple/circles 4.5 µm; blue/sq. 5.5 µm). Reproduced from [178]. (b) High density nanowires are contacted by nickel electrodes. The inset displays the histogram of channel lengths of individual nanowires after silicidation for a device with 2.5 µm inter-electrode spacing. Reproduced from [178].