Table 2.

The instruction set of the designed neural network processor

Instruction type	Instruction	Function
Integer computation	add_r $s1 $s2 $dst	RF[$dst] = RF[$s1] + RF[$s2]
	sub_r $s1 $s2 $dst	RF[$dst] = RF[$s1] - RF[$s2]
	mult_r $s1 $s2 $dst	RF[$dst] = RF[$s1] $\times$ RF[$s2]
	addi_r $s1 Simm $dst	RF[$dst] = RF[$s1] + SignExt[imm]
	subi_r $s1 Simm $dst	RF[$dst] = RF[$s1] - SignExt[imm]
	muli_r $s1 Simm $dst	RF[$dst] = RF[$s1] $\times$ SignExt[imm]
Fixed-point computation	add_e $s1 $s2	DM[$s1] + DM[$s2]
	sub_e $s1 $s2	DM[$s1] - DM[$s2]
	mult_e $s1 $s2	DM[$s1] $\times$ DM[$s2]
	addi_e $s1 $s2	DM[$s1] + FPSignExt[imm]
	subi_e $s1 $s2	DM[$s1] - FPSignExt[imm]
	muli_e $s1 $s2	DM[$s1] $\times$ FPSignExt[imm]
	wr_alu $s1	DM[$s1] = alu_result
	wr_acf1 $s1 $s2	DM[$s1] = DM[$s1] = ACF(alu_result, DM[$s2])
	wr_acf2 $s1 $s2	DM[$s1] = DM[$s1] = ACF(acc_result, DM[$s2])
	wr_acc $s1 $s2	DM[$s1] = DM[$s1] = acc_result
	rst_acc	Reset ALU accumulator to zero
Setup	iset_acf code	Set activation function to sigmoid, tanh, or ReLU
	sw_imm	Swap ALU inputs
	done	Assert processor done flag for 1 clock cycle
	rd_dm $s1	Read DM[$s1] and write to processor output port
Control	beq $s1 $s2 offset	Branch to PC+offset if RF[$s1] == RF[$s2]
	bneq $s1 $s2 offset	Branch to PC+offset if RF[$s1] != RF[$s2]
	jump jump_address	PC = jump_address
	jump_reg $s1	RA = PC+1; PC = RF[$s1]
	jump_return	PC = RA
	nop	No operation