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. 2022 May 10;12:7681. doi: 10.1038/s41598-022-11946-7

Figure 2.

Figure 2

SEM image of etch holes in fabricated InGaAs PD based on the InP substrate: (a) The surface of the etch holes array. (b,c) The cross section of side wall covered with composite passivation layer in [100] and [010] direction. (d) A magnified view of a side wall of the outline area on the left shows side wall covered with Si3N4 (158 nm) and SU-8 (1.15 μm).