Table 1.
Works | [9] | [10] | [19] | [20] | This Work |
---|---|---|---|---|---|
Power supply | 3.3 V/1.8 V | 3.3 V/1.8 V | N/A | 2.5 V/1.2 V | 2.5 V/1.2 V |
Process [nm] | 180 CMOS | 180 CMOS | 55 CMOS | 90 CMOS | 65 CMOS |
Total area [mm2] | N/A | 19.32 (1) | 0.1 (1) | 2 (1) | 6.9/channel (1) |
Structure | LDAC (2) | LDAC (2) | NLDAC (2) | Hybrid (2) | LDA (2) |
No. of Channel | 1 | 1 | 1 | 1 | 4 |
[MHz] | 1000 | 2500 | 2000 | 1300 | 1000 |
Spur reducing | Auxiliary (3) | Auxiliary (3) | N/A | N/A | Automatic detection |
SFDR [dB] | −59 (4) | −58 (4) | −55.1 | −52 | −59.9 (4) |
Power | 0.7 W@ 1 GHz (5) | 1.9 W@ 1 GHz (5) | 0.13 W@ 2 GHz (5) | 0.35 W@ 1.3 GHz (5) | 0.6 W/channel @1 GHz (5) |
(1) Including pads. (2) NLDAC, LDAC and Hybrid are the abbreviations of nonlinear DAC, linear DAC and hybrid DAC respectively. (3) Spectrum analyzer and other instruments are required. (4) After reduced. (5) Total power consumption of DDS.