Algorithm 1. Capacitance extraction algorithm from the 3D footprint.

1- Switch off the transmission gate and obtain the output curve versus the value of sweeping reference capacitance (number of pulses versus CR). 2- Calculate the output of the chip for CR = 400 fF from the curve obtained in step 1. 3- Turn on the switch and obtain the number of pulses versus the CR curve. 4- For the calculated output in step 2, calculate the amount of shift to right. The shifted value is the offset capacitance of the IDE, CIDE. 5- Calculate the number of pulses for CR = 400 + CIDE that was obtained in step 4. 6- For the calculated output in step 5, calculate the amount of shift to right after putting the samples. The shifted value is the capacitance increase due to the presence of samples on the electrodes. 7- Repeat the steps for all the next obtained curves to achieve a time-resolved capacitance plot (as shown in Figure 12).