FIGURE 4.
Overview of the hardware implementation of our HFO detection system. (A) Abstract schematic of the pre-processing and configuration pipeline. Signals from the electrodes pass through amplification, filtering and analog delta modulation (ADM) delta modulation to reach the spiking neural network (SNN). The chip can be configured, send and receive data through an FPGA daughterboard and via a personal computer; note that this is not required to be online during the operation of the chip. (B) Micrograph of the eight channels of analog headstage implemented on the top-left corner of the chip (the image is rotated 90° clockwise) and they are located right next to one of the four neural cores.