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. 2022 Jul 8;12:11691. doi: 10.1038/s41598-022-14804-8

Figure 1.

Figure 1

A schematic of the C17 circuit with a fault on output of the third NAND gate for a given input/output pair. In “Benchmarks on synthetic instances: spectral gaps and simulated annealing schedules” section, we generate new random circuits by replacing each NAND gate with a randomly selected two input logic gate.