Figure 3.
The first- (a, b) and second- (c, d) generation ASICs incorporating multiple mux switches for interfacing to 2D and 1.75D transducer array elements. (a) First-generation ASIC unit cell, (b) complete first-generation device, (c) complete second-generatation ASIC, (d) second-generation ASIC unit cell CAD layout ((b) adapted from [30], (c-d) adapted from [40]).
