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. 2021 Feb 23;3(8):2117–2138. doi: 10.1039/d0na01043j

Performance parameters of 2D MoS2-FETs based on wafer-scale MoS2 films.

MoS2 Configurations Dielectrics L (μm) μ FE (cm2 V−1 s−1) I on/Ioff ratio SS (mV dec−1) Ref.
Monolayer on sapphire by CVD Top-gated HfO2 3.5 0.1–3 >106 130 8
4-Inch monolayer by CVD ITO back-gated Al2O3 6 ∼55 1010 13
Few-layer by exfoliation Back-gated SiO2 2 167 ± 20 14
8-Inch monolayer by MOCVD Back-gated SiO2 10 0.47 5.4 × 104 18
4 inch-scale by MOCVD Back-gated SiO2 7–12 104–107 21
6-Inch monolayer by CVD Back-gated SiO2 1 6.3–11.4 105–106 24
Monolayer by Au-assisted exfoliation Top-gated SiO2 22.1–32.7 ∼107 100 30
2-Inch monolayer by CVD Back-gated SiO2 30–60 ∼40 ∼106 31
2-Inch continuous by CVD Top-gated HfO2 10–100 70 107 150 32
4-Inch monolayers by CVD Back-gated SiO2 10 ∼70 ∼109 33
Monolayer by APCVD Back-gated Al2O3 0.033 5.8 × 105 34
Wafer-scale monolayer by CVD Back-gated SiO2 20 1.2 35
Monolayers on Au by CVD Back-gated SiO2 5 ∼11.2 7.7 × 105 37
Continuous monolayer by CVD Back-gated SiO2 1 ∼9.8 3.1 × 106 40
2-Inch by PLD and sulfurization Top-gated HfO2 90 8.85 ∼105 50
Monolayer by MOCVD Back-gated SiO2 10 21.6 51
Monolayer on 2-inch sapphire Top-gated Al2O3 15 ∼0.76 ∼104 52
3.5 × 3.5 cm2 monolayer by CVD Back-gated SiO2 20 1.3 × 10−2 ∼104 8300 55
2-Inch monolayer by MOCVD Back-gated SiO2 10 21.6 56
Monolayer by MOCVD Ti/Au back-gated Al2O3 10 3.4 ± 0.3 107 57
Monolayers by VLS Back-gated SiO2 21.1 107–109 59
1.5 × 1.5 cm2 monolayer by VLS Back-gated SiO2 1.48 33 >108 980 60
Few-layer on sapphire by ALD Top-gated Al2O3 25 0.56 106 68
Continuous monolayer by CVD Top-gated Al2O3 6.44 >108 76
10 × 10 mm2 monolayer by CVD Back-gated HfO2 6 118 108 77
Monolayer and bilayer by CVD Dual-gated Y2O3/HfO2 10 1–9 >106 90
Monolayer by CVD Back-gated SiO2 2.87 3.2 × 106 96
Bilayer by CVD Dual-gated HfO2 10 32.5 ∼800 99