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. Author manuscript; available in PMC: 2023 Mar 17.
Published in final edited form as: J Neural Eng. 2022 Mar 17;19(2):10.1088/1741-2552/ac572c. doi: 10.1088/1741-2552/ac572c

Table 1.

Module states and corresponding switch states and module output voltage

Module state Transistor switch state Module output
Q i1 Q i2 Q i3 Q i4 V i
0 Off Off Off Off {−VCi, 0, VCi}
1 On Off On Off V Ci,
2 Off On Off On VCi
3 On Off Off On 0 (bypass)
4 Off On On Off 0 (bypass)
5 Off On Off Off {−VCi, 0}
6 Off Off On Off {0, VCi}
7 On Off Off Off {0, VCi}
8 Off Off Off On {−VCi, 0}