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. 2022 Sep 22;22:253. doi: 10.1186/s12911-022-01994-4

Table 3.

Garbled AND gate

Input w0 Input w1 Output w2 Garbled value
k0w0 k0w1 k0w2 Enck0w0,k0w1(k0w2)
k0w0 k1w1 k0w2 Enck0w0,k1w1(k0w2)
k1w0 k0w1 k0w2 Enck1w0,k0w1(k0w2)
k1w0 k1w1 k1w2 Enck1w0,k1w1(k1w2)