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. 2022 Apr 12;15(1):9. doi: 10.1007/s12200-022-00012-9

Fig. 12.

Fig. 12

Fabricated structure of a TOPS with geometrical design optimization for tuning efficiency improvement [59]. a Physical layout of the fabricated TOPS with SEM photographs of multi-section Clothoid bend structures and waveguide array with alternating widths. b Microphotograph of a fabricated TOPS test chip. c Vertical and d horizontal cross-section of the TOPS with simulated temperature profile at the center of the silicon waveguide