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. 2022 Dec 21;14(1):8. doi: 10.3390/mi14010008

Figure 2.

Figure 2

(a) Architecture of dual basis RS encoder. (Reprinted from [26], Copyright 2009, with permission from IEEE). (b) Circuit implementation of the vector string/parallel divider RS encoder. (Reprinted from [27], Copyright 2019, with permission from Elsevier). (c) Architecture of variable-rate RS encoder. (Reprinted from [30], Copyright 2011, with permission from Springer).