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. Author manuscript; available in PMC: 2023 Sep 29.
Published in final edited form as: IEEE J Solid-State Circuits. 2022 Sep 29;57(11):3243–3257. doi: 10.1109/jssc.2022.3204508

Fig. 7.

Fig. 7.

Timing diagram of the two-step (coarse/fine) DSL operation in channel-selective inference mode. (a) The coarse EDO cancellation using 9-bit binary search is performed in the first sampling period in each feature extraction window. (b) The ΔΣ fine loop for residual EDO cancellation operates for the rest of the feature extraction window.