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. Author manuscript; available in PMC: 2023 Sep 29.
Published in final edited form as: IEEE J Solid-State Circuits. 2022 Sep 29;57(11):3243–3257. doi: 10.1109/jssc.2022.3204508

TABLE II.

Comparison with the State-of-the-Art Neural Interface SoCs with On-Chip ML

Parameter JSSC’15 [5] JSSC’18 [15] JETCAS’18 [16] ISSCC’18 [17] ISSCC’20 [18] JSSC’20 [19] TBioCAS’21 [20] VLSI’21 [21] JSSC’22 [22] This Work
Process (nm) 180 180 65 130 65 40 180 28 40 65
Supply Voltage (V) 1.8/1 1.8 0.8 1.2 1.2 0.58 1.5 0.5 1.1/0.7 1.2
# Recording Ch. 16 16 32^ 32 8 14^ 8 8^ 16 256
# Stimulation Ch. 1 16 - 32 1 - 2 - 1 16
Area/ch.* (mm2) 1.563 0.95 0.031^ 0.237 0.244 0.182^ 0.729 0.013^ 0.13 0.014
Energy Efficiency (μJ/class) 2.73 64§ 0.0412^ 178.7§ 0.036^ 170.9^ 174.4§ 0.0015^ 0.97 0.227
Memory (kB) 64 - 1 96 - 35.8 64 0.2 134 3.17
Classifier D2A-LSVM Ridge Regression XGB-DT EDM-SVM BrainForest NL-SVM Coarse (Th.) Fine (LS-SVM) LR + SGD GTCA-SVM NeuralTree
Feature Set SE FFT, ApEn LL, POW, VAR, SE PLV, CFC, SE RAF Neurons SE MODWT-KDE SE, LL SE PLV, PAC, SE, HFOR, LL, LMP, Hjorth
Dataset (# Patients) MIT (14) Local (5) iEEG (20) EU-iEEG (-) EU-iEEG (-) MIT (24) MIT (23) UoM (3) MIT (24) MIT (24) MIT (24) iEEG(6)
Sensitivity (%) 95.7 96 83.7 100 96.7 96.6 97.8 97.9 97.5 100 95.6 94
Specificity (%) 98 100 88.1 0.81FP/hr 0.8FP/hr 0.28FP/hr 99.7 98.2 98.2 99.5 96.8 96.9
Latency (s) 1 0.76 1.1 <0.1 - 0.71 <0.3 2.6 1.6 0.74 <1
*

Estimated based on SoC area and # of recording channels

Including data storage

^

Digital back-end only

NeuralTree (2.93kB), FIR (0.2kB), and SPI (0.04kB)

§

Estimated based on AFE and DBE power consumption