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. Author manuscript; available in PMC: 2017 Mar 22.
Published in final edited form as: Phys Med Biol. 2016 Apr 6;61(9):3500–3526. doi: 10.1088/0031-9155/61/9/3500

Figure 7.

Figure 7

Phase pattern schemes at SDM level for an SDM with six stacks: compared to the default sensor die clocking where no phase shift is applied (a) is a sensor die clock pattern with 180° clock phase shifts for complete stacks (stack level) to obtain a checkerboard pattern (b).