2D materials readiness for the transistor performance breakthrough

Qing Zhang; Chunsen Liu; Peng Zhou

doi:10.1016/j.isci.2023.106673

. 2023 Apr 19;26(5):106673. doi: 10.1016/j.isci.2023.106673

2D materials readiness for the transistor performance breakthrough

Qing Zhang ¹, Chunsen Liu ^1,^2,^∗, Peng Zhou ^1,^2,^∗∗

PMCID: PMC10192534 PMID: 37216126

Summary

As the size of the transistor scales down, this strategy has confronted challenges because of the fundamental limits of silicon materials. Besides, more and more energy and time are consumed by the data transmission out of transistor computing because of the speed mismatching between the computing and memory. To meet the energy efficiency demands of big data computing, the transistor should have a smaller feature size and store data faster to overcome the energy burden of computing and data transfer. Electron transport in two-dimensional (2D) materials is constrained within a 2D plane and different materials are assembled by the van der Waals force. Owning to the atomic thickness and dangling-bond-free surface, 2D materials have demonstrated advantages in transistor scaling-down and heterogeneous structure innovation. In this review, from the performance breakthrough of 2D transistors, we discuss the opportunities, progress and challenges of 2D materials in transistor applications.

Subject areas: Applied sciences, Materials science, Nanomaterials

Applied sciences; Materials science; Nanomaterials

Introduction

The continuous scaling down of the transistor size drives the performance booming of integrated circuits. However, with the technology node of the transistor below 5 nm, the state-of-the-art transistor structure (Fin field-effect-transistor, FinFET) becomes unsustainable for performance enhancement. The scaling down of FinFET needs taller and thinner Fin channels. The tall Fin and aggressive Fin pitch will lead to sidewalls damages to Fins¹ and the mobility of the silicon material with a thickness below 3 nm will also be significantly degraded.²^,³ What’s more, the lattice mismatch issues between different bulk materials have also limited the development of novel heterostructure transistors.⁴ Heterostructure transistors with optimized electrical band structure can better support device structure innovation and performance breakthroughs. For example, heterostructure can advance the band-to-band tunneling efficiency in the tunneling FET (TFET) and enables steeper subthreshold swing (SS). Therefore, a material system with good electrical characteristics in ultrathin thickness and owning flexible heterostructure integration ability will be favorable for breaking the transistor performance bottleneck.

Except for the transistor scaling down issue, the energy and time consumption of the system is also limited by the data shuttle efficiency.² The most widely used computer architecture is the von Neumann architecture where the computing and memory modules are physically separated. The data shuttle rate between the computing module and the memory module is limited by this architecture, leading to large energy and time consumption when the processing data is big, even larger than the consumption of the computing itself.⁵ The volume of high-speed volatile transistor memory is too small to memorize all the data, whereas the high-density non-volatile transistor memory is too slow to timely stored or recall data. Although the different volatile memory chips can be connected through silicon via interconnects to accelerate the data transfer process,⁶ the limited connection density of silicon via is not adequate for highly energy-efficient computing.⁷^,⁸ An ultrafast non-volatile transistor memory technology that supports high-density integration is needed.

2D materials are covalently bonded in a plane with a dangling-bond-free surface, and a single layer (thickness below 1 nm) can be easily achieved from a bulk crystal.⁹ Because the neighboring layer in 2D materials is connected only by a weak van der Waals (vdW) force, the electrical characteristics of 2D materials will not degrade when their thickness thins to monolayer. Benefiting from this unique characteristic, the electron transportation is tied to a thin channel¹⁰ which means that the space charge region in the drain/source will not expand along the channel direction. This transportation process is similar to the silicon-on-insulator technology and hence the 2D materials transistor can be immune short channel effect. What’s more, the different 2D materials can be assembled to form various heterostructures by a van der Waals stacking technology because of their dangling-bond-free surface. The 2D materials are a big material system and can provide enough options for the device structure and function design. It is predicted that over one thousand kinds of 2D materials can be easily exfoliated and various 2D materials demonstrate abundant properties,¹¹ such as electronic,¹²^,¹³^,¹⁴ photoelectric,¹⁵ magnetic¹⁶ and ferroelectrics¹⁷^,¹⁸ properties. With good electrical performance in small feature sizes and flexible heterostructure constructing ability, 2D materials are possible to solve the performance bottlenecks of the transistor.

In this article, we review the performance breakthrough of 2D transistors. The discussion of the 2D transistors is focused on the scaling down issue, contact optimization, ultrathin gate oxide, steep subthreshold swing (SS), and ultrafast charge storage speed. Finally, we discuss the challenges that hinder 2D transistors from large-scale applications.

Discussion and results

2D materials are different from silicon in the structure, which is covalently bonded in the plane and adjacent layers are linked only by the vdW force. Therefore, the basic fabrication processes and the performance modulation methods of the 2D transistors are not like the silicon metal-oxide-semiconductor FET (MOSFET) integration process. The ultrathin body and dangling-bond-free surface make it challenging to form good contact and high-quality high-κ dielectric in the 2D transistors. The flexible assembly of different 2D materials has broadly inspired the innovation of new mechanism transistors, which allow the 2D transistor to break the theoretical performance boundary of the silicon MOSFETs. In summary, the introduction of 2D materials has brought both opportunities and challenges in the performance breakthrough of transistor technology.

The ultrasmall gate-length transistor demonstration

It’s well-known that the performance of transistors can be continuously optimized according to a generalized scaling theory proposed by Dennard in 1974.¹⁹^,²⁰ According to this theory, the transistor’s lateral dimensions, transistor junction depth, oxide thickness and supply voltage are reduced by K⁻¹ (K>1) and the substrate doping concentration is increased by a factor of K. Through the scaling down the size of the transistor, the chip density will increase by a factor of K², and the device delay time and power consumption will reduce by a factor K⁻¹ and K⁻², respectively. However, for shorter channel devices, a series of short-channel effects arise that result in the failure of the theoretical prediction, such as the source/drain charge depletion region extending along the channel direction, and the drain-induced barrier lowering (Figure 1A). Although the FinFET technology has extended the technology node to “3 nm” (not the physical gate length of the transistor), the structure of the next-generation transistor has to change because the mobility of silicon FETs degrades quickly when the channel thickness is below 3 nm.²¹^,²²

Essentially, the scaling issues of silicon transistors are caused by the electrical performance degradation of the thin channel materials and the gate modulation being out of control to the short channel. The transistors with ultrathin 2D materials as channel material do not bother by these problems. The electrical properties of 2D materials will not degenerate even with a monolayer thickness. 2D materials, such as graphene, black phosphorus and transition-metal-dichalcogenides (TMDs), all have demonstrated good electrical properties with a very thin thickness. The graphene transistor is the first demonstrated 2D transistor and shows very high mobility but a limited on/off current ratio because of its zero bandgap.²³^,²⁴ The black phosphorus transistor also shows high mobility and has an appropriate bandgap and is easily oxidized in the atmospheric environment.²⁵^,²⁶ The TMDs have contained abundant materials and various electronic band structures, some of which show both large enough bandgap (1–2 eV) and good mobility (over 100 cm⁻²V⁻¹s⁻¹) for transistor applications,²⁷^,²⁸^,²⁹^,³⁰^,³¹ like the MoS₂ and WSe₂. As for the short-channel transistor demonstration, many works have experimentally proven that planar 2D transistors can be well worked with a very short channel length (less than 10 nm) which is beyond the ability of the planar silicon transistors.³²^,³³ Because the ultrathin channel of the 2D transistor is on an insulator substrate, the carrier charge transportation is constrained within the 2D plane and no charge depletion region can extend along the channel on an insulator substrate (Figure 1B).

Particularly, some works have skillfully demonstrated that the gate length of a 2D transistor can be scaled below 1 nm. Desai et al.³⁴ have fabricated a 1-nm-gate-length MoS₂ transistor. In this work, a carbon nanotube (CNT, diameter of ∼1 nm) has been chosen as the gate terminal and ZrO₂ serves as the high-κ dielectric. The 1 nm-length CNT was located by the scanning electron microscopy and optical microscope and then the bilayer MoS₂ has been transferred above the CNT gate. The final device structure is shown in Figure 1C. It should be noted that the length between the source and drain metal contact is hundreds of nanometres, but the MoS₂ that not controlled by the CNT can also serve as the source/drain interconnects because these parts’ MoS₂ can be modulated to be good conductor by the voltage bias of silicon substrate. The ultrashort gate length device shows impressive electrical performance with a near-ideal SS of ∼65 mV/dec and a switching ratio of ∼10⁶. Except for using the CNT as an ultrashort gate, Jiang et al.³⁵ have proposed a vertical-channel vdWs transistor in which the channel length can be controlled by the thickness of the deposited metal or dielectric materials. Subsequently, Wu et al.³⁶ further developed this technology and demonstrated a vertical channel transistor with the edge of graphene as the side-wall gate. As Figure 1D has represented, the length of the gated vertical MoS₂ channel is around 0.34 nm (the thickness of graphene is around 0.34 nm).

Besides the planar transistor, the multibridge channel (MBC) structure based on the gate-all-around (GAA) technology³⁷^,³⁸^,³⁹ has been developed to realize the transistor with a feature size below 3 nm. For the MBCFET, 2D materials have provided a self-aligned edge-contact technology which paves the way toward higher-levels-stacked ultrathin MBCFET.⁴⁰^,⁴¹ In consideration of the ultrathin thickness of 2D materials, it is predicted that the channel material of MBCFET will switch to 2D materials when the technology node comes to 1 nm.⁴²

Alternative scaling route: Single logic transistor

Digital circuits contain massive logic gates and a basic logic gate needs several transistors to implement a logic function, for example, two transistors connected in series/parallel to realize the AND/OR logic functions. The smaller feature size of transistors can allow more computing cells to integrate into the chip. Alternatively, if the same logic functions can be carried out with fewer transistors, more functions will be integrated into the chip.

One promising solution is a reconfigurable logic device, where the devices’ function is not fixed and the same device can carry out different logic functions with various configurations.⁴³^,⁴⁴^,⁴⁵^,⁴⁶ Compared with traditional logic gates, the reconfigurable logic device shows many more flexible logic functions. However, the function configuration usually needs additional area (e.g., additional regulate electrodes) which means the scaling down of a single reconfigurable device has more difficulty than that of the basic transistor structure. Liu et al.⁴⁷ have experimentally demonstrated that a double-gated 2D transistor can realize logic computing (e.g., AND, OR) and there is no need for integrating additional regulated electrodes (Figure 2A). For a silicon transistor, only the top surface of the transistor can be regulated, therefore two top-gated transistors are needed to implement the two inputs logic gate (Figure 2B). In the single logic transistor, the top and bottom gates can regulate channel surfaces and serve as two input terminals. Figure 2C has comparing the mechanism difference between the single logic transistor and the traditional transistor. Subsequently, Zeng et al.⁴⁸ further demonstrated that a single WSe₂ double-gated transistor has multiple logic functions (AND, XNOR) and these functions are electrically switchable by the drain voltage. As Figure 2D has shown, using this reconfigurable single logic transistor as the pixel processing unit, the image processing array can perform two different image tasks and the consumption of transistors of this image processing unit is less than 16% of traditional circuits. A series of works have demonstrated the logic functions of this single logic transistor can be reconfigurable by other factors, such as photo illumination, working temperature.⁴⁹^,⁵⁰

Alternative scaling route: single logic transistor

(A) The schematic device structure of a single logic transistor. Reproduced with permission from (Liu et al., 2019) Copyright© 2019, Springer Nature.

(B) The area efficiency advantage of the single logic transistor. Reproduced with permission from (Liu et al., 2020) Copyright© 2020, Springer Nature.

(C) The mechanism comparison between the logic transistor and the traditional silicon transistor. Reproduced with permission from (Liu et al., 2019) Copyright© 2019, Springer Nature.

(D) Logic function switchable single transistor and its image processing application. Reproduced with permission from (Zeng et al., 2022) Copyright© 2022, Springer Nature.

The contacts optimization of 2D transistors

In the silicon MOSFET fabrication process, ideal nonrectifying contacts can be formed by heavy doping and silicon-metal alloy technology. When it comes to atomic thin film 2D materials with dangling bond free surface, there is still no good method for non-destructive and stable doping of few layer 2D materials. Most doping method of 2D materials is based on a solution or gas atmosphere, and the doping process is not compatible with large-scale integration.⁵¹^,⁵²^,⁵³^,⁵⁴ The unique layered structure of 2D materials raises challenges in the formation of low-resistance contact. Three types of metal-2D semiconductor contact are predicted by ab initio density-functional theory calculations, covering type 1, metals with very weak adhesion with 2D materials; type 2, medium adhesion; and type 3, strong adhesion.⁵⁵^,⁵⁶ In type 1, there is a large Schottky barrier because the metal and the 2D materials do not contact well; in type 2, the tunnel barrier is negligible but there are many overlap states; in type 3, metal atoms strongly perturb the band structure of 2D materials and results in the metalized 2D materials (Figure 3A). Although the theory in the early stage has predicted that type 3 could form a stable and low-resistance alloy contact, the experimental results are not satisfying.

In the 2D transistor fabrication process, the metal-2D semiconductor junctions are chosen to modulate the contact performance. In the early studies, researchers generally believe that the Schottky barrier height is the key factor that domains the contact resistance of metal-2D semiconductors and a smaller barrier can guarantee better contact. The height of the Schottky barrier is the absolute difference between the work function of metal and the electron affinity (ionization potential) of the n-type (p-type) 2D materials. There is plenty of research showing that the 2D transistors can be modulated to behave in different polarity by tuning the contact metal work function.¹²^,⁵⁷^,⁵⁸ Chuang et al.⁵⁹ even reported that the well-known n-type MoS₂ transistor can be modulated to p-type when high work function materials (MoO_x) are chosen as contacts. However, the MoS₂ in this work is very thick (tens of nanometers) and typically the monolayer MoS₂ with high work function metal contact materials is still n-type. For most monolayer 2D material transistors with contact metal deposited by the physical vapor deposition method, the Schottky barrier height seems pinned to a fixed position near the semiconductor bandgap and not sensitive to the work function of the contact metal.

Further studies show that the metal deposition process will damage the few-layer materials and lead to the Fermi-level pinning effect. Liu et al.⁶⁰ have developed a metal transfer technology to form damage-free metal-2D materials junctions and Figure 3B has shown the good contact interface that formed by this transfer technology. In their work, the metal deposition damage issue has been solved and the transfer characteristics of transistors with monolayer channels can still be effectively tuned by the work function of transferred metal materials. The metal-transferred technology has effectively avoided the Fermi-level pinning effect, but the transferred method has a very low alignment precision which is not suitable for high-density integration. Kwon et al.⁶¹ have proposed another defect-free metal-2D material contact integration method that supports patterned metal deposition. A 10-nm-thick selenium layer was deposited by thermal evaporation in a high vacuum (<10⁻⁹ torr) and this process shows no damage to the surface of 2D materials. Subsequently, the contact metal (e.g., golden) can be deposited by electron-beam evaporation and the selenium buffer layer can be removed by annealing at 150°C in a high vacuum (<10⁻⁹ torr). As Figure 3C has shown, intimate and defect-free contacts can be formed and the transfer characteristics of 2D transistors can also be effectively tuned by the work function of deposited metal materials.

Although the Fermi-level pinning effect has been decreased by the innovative construction methods of metal-2D materials junction, the reported drive current and the contact resistance of the 2D transistors are still not satisfying. Shen et al.⁶² reported a semimetal-2D materials contacts technology in 2021, which shows impressive ultralow contact resistance that is close to the quantum limits (Figure 3D). Several other groups have quickly verified this technology and all of them reported improved device performance.⁶³^,⁶⁴ In the first reported work, semimetal bismuth has been used as contacts on several 2D semiconductors, covering MoS₂, WS₂ and WSe₂. Utilizing the semimetal as the contact, the metal-induced gap states are sufficiently suppressed and degenerated states are formed in the contact region. The bismuth-contacted monolayer MoS₂ transistor has demonstrated a contact resistance of 123 Ω μm and drive current up to 1135 μA/μm.

Besides the geometry of the top contacts, the 2D transistor has developed a unique edge contact geometry.⁴⁰^,⁶⁵^,⁶⁶ Surprisingly, 1D edge contact is enough to provide good contact and transmit a large drive current, which means the contact area of the 2D transistor will not be a limitation in ultrasmall feature size.

The integration of ultrathin HIGH-κ dielectric on 2D materials

The dangling-bond-free surface of 2D materials not only impacts the quality of the contact but also leads to the dielectric integration challenge. In the state-of-the-art integration circuit fabrication process, the high-κ gate oxide is deposited by the atomic layer deposition (ALD) technology and the small equivalent oxide thickness (EOT) of high-κ dielectric will advance the transistor performance. The ALD is a gas-phase chemical process and two precursors react with the surface of the channel material one at a time in a sequential and self-limiting manner. Therefore, the absence of dangling bonds will make the precursors hard to attach to the 2D materials. Figure 4A has briefly represented a Al₂O₃ deposition process by ALD on 2D materials. Typically, the directly deposited dielectric by ALD on a 2D material has a rough surface and pin-holes within the dielectric. Although there are some 2D dielectric materials, like hBN, that can directly transfer on the channel as good dielectric, the relatively small dielectric constant and the challenge in patterning dielectric make them not suitable for high-density integration. Integrating ultrathin high-κ dielectric on 2D materials is important for reducing power consumption and elevating the stability of the 2D transistors.

To improve the absorption of precursors on the dangling-bond-free surface, pretreatment of the surface of the 2D material is necessary. In the early stage, there are various pretreatment schemes to improve the quality of ALD high-κ dielectric on 2D materials, such as ultraviolet ozone and oxygen plasma. These methods will destroy the top layers of the channel materials and are not suitable for 2D materials with few layers. To avoid the damage of pretreatment to the channel, a remote oxygen plasma retreatment is developed where the ultralow energy plasma is physically adsorbed on MoS₂ surfaces without making the flakes oxidise.⁶⁷ But the absorption of the remotely flowed oxygen plasma cannot be well controlled. In general, moderate damage to the perfect surface of the 2D materials can make the dielectric integration easier but these methods are not suitable for the few-layer 2D materials. To stably realize large-scale sub-10 nm high-κ dielectric integration, an ultrathin metal (metal oxide) seeding layer method has been proposed.⁶⁸ Before the ALD high-κ dielectric deposition, an ultrathin metal (∼1 nm) seeding layer is deposited on the channel material by physical vapor deposition. These metals should be easy to oxide (e.g. aluminum, yttrium) and after the oxidation, the high-κ dielectric can be deposited by a standard ALD process. Alternatively, adopting metal oxide as the seeding layer is also working well.⁶⁹

In consideration that the quality of the metal oxidation buffer layer is not as good as the high-κ dielectric grown by ALD, the existence of the buffer layer makes the thickness of the dielectric hardly scale below 3 nm. Li et al. have explored a monolayer molecular crystal 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA) (∼0.3 nm) as the seeding layer which can allow the HfO₂ scale below 3 nm and the EOT of the dielectric stack can be as low as 1 nm.⁷⁰ A highly crystalline and uniform monolayer PTCDA can be self-limited epitaxial grown on the 2D materials and the carbonyl functional groups in PTCDA can function as sites for ALD nucleation and growth (Figure 4B). In consideration that the monolayer PTCDA is a low-κ material, further scaling the EOT of the dielectric stack below 1 nm will be challenging. Li et al.⁷¹ have discovered that the 2D materials Bi₂O₂Se can be layer-by-layer oxidized to form an atomically thin gate dielectric (Bi₂SeO₅). As Figure 4C has shown, similar to the Si/SiO2, the Bi₂O₂Se/Bi₂SeO₅ has a very good interface and the native oxide Bi₂SeO₅ can be also selectively etched away. Because the dielectric constant of Bi₂SeO₅ is around 21, this new technology can integrate a high-κ dielectric with an EOT scale to 0.9 nm. Subsequently, Zhang et al.⁷² have further optimized this technology and realized the selective oxidation through a lithography-compatible ultraviolet-assisted intercalative oxidation of the Bi₂O₂Se. The EOT of the dielectric Bi₂SeO₅ on the Bi₂O₂Se has also successfully decreased to 0.5 nm.

The steep SS 2D transistors

Besides the scale-down issue of the transistor feature size, the scaling of the supply voltage is also a challenge in the advanced technology node. In a conventional silicon MOSFET, the potential barrier of the source/channel is regulated by the gate voltage and the electron energy distribution of silicon (thermal Boltzmann distribution) makes the SS of the transistor cannot be below 60 mV/dec at room temperature. Limited by the minimum SS value, the supply voltage shrink-down is stagnant and the leakage current of an ultrathin dielectric becomes unacceptable.⁷³^,⁷⁴ For the 2D transistor, this problem is also existing because the electron energy distribution of most 2D semiconductors is still Boltzmann distribution (Figure 5A). To break this minimum SS limitation, several new FET mechanisms have been researched, such as tunneling FET (TFET)⁷³^,⁷⁴ and negative capacitance FET (NCFET).⁷⁵ Compared with traditional bulk materials, 2D materials have strong advantages in the innovation of new mechanisms. The abundant 2D materials have provided rich electronic band structures which can provide more design space from band engineering. The flexible vdWs heterostructure assembling can also guarantee the designed band structure can be realized. The outbreak of various new steep SS mechanisms 2D transistor technologies has demonstrated the value of 2D materials and vdWs heterostructures.

TFET is one of the alternatives to the traditional MOSFET, the device mechanism is a band-to-band tunneling process where the hot electrons in the Fermi tail can be blocked by the bandgap. In a silicon TFET, the band alignment is realized by the different doping levels of the source, channel and drain region. Although 2D materials have enables more possibilities. Utilizing heterostructures can construct reasonable band structures, but the situation of interface could be challenging. The electronic band structures of 2D materials can be modulated by their thickness, for example, the bandgap of black phosphorus is varying from 0.3 eV (bulk) to 2 eV (monolayer). Kim et al.⁷⁶ have reported a natural homogeneous black phosphorus TFET based on this bandgap modulation effect and there are no interface issues. Single black phosphorus with both bulk and monolayer regions was chosen to fabricate TFET, the bulk region functions as the source and the monolayer region covered with hBN and graphite functions as the channel and drain, respectively (Figure 5B). Both the n-type and p-type modes can realize average SS values over 4 decades of currents below 25 mV/dec at room temperature. There are also 2D-material-based NCFETs but they also have a hysteresis issue.⁷⁷^,⁷⁸^,⁷⁹

Except for the steep SS mechanisms that already realized by the traditional bulk materials system, there are new mechanisms based on 2D materials have been proposed. Xiong et al.⁸⁰ have proposed a transverse tunneling FET mechanism, which is not the same as the TFET. As Figure 5C has shown, the band-to-band tunneling in a TFET is occurring in the direction along the channel, whereas the tunneling current in the transverse tunneling FET is perpendicular to the channel. Although this transverse tunneling current made the SS could below 60 mV/dec, the leakage current (several microamperes) of the channel is not satisfying. Utilizing the unique Dirac point in the electronic band structure of graphene, Qiu et al.⁸¹ have put forward a new mechanism Dirac-source FET based on the graphene/CNT heterostructure. Different from the TFET, Dirac-source FET uses the Dirac point to cut off the Fermi tail to prove that a small SS and thermal emission at the graphene/CNT interface guarantee a large driving current (Figure 5D). For now, this is the most successful steep SS mechanism that showed the greatest balance in performance for both a small SS and a large driving current. This new mechanism is also verified in the graphene/MoS₂ heterostructure.⁸²

The ultrafast floating-gate transistor

In integrated circuits, the transistor is not only functions as a switch but also used to store data. The mainstream memory technologies are all based on transistor structure. The high-speed memories are volatile memory, covering static random access memory (SRAM) and dynamic random access memory (DRAM). Both of them are based on transistor technology and have limited volume because of their complex structures, SRAM is built with six transistors and DRAM has a 1 transistor-1 capacitor structure. Flash memory is representative of high-density non-volatile memory (data can be stored for more than 10 years) and its basic structure is a simple floating-gate transistor where a floating gate is inserted into the gate dielectric functions as the charge storage. Figure 6A has indicated that the big challenge in all these charge memory technologies is the contradiction between the programming speed and the charge storage ability. The volatile memories have ultrafast programming speed (SRAM∼1 ns, DRAM∼10 ns) but the data only maintains while the device is powered and their storage volume is also limited. Non-volatile memory has 10 years of data storage ability without a power supply and is high-density, but the accessing speed is limited to ∼100 $μ$ s.⁸³ The floating-gate transistor support high-density integration and the programming speed breakthrough of a floating-gate transistor is important.

There are plenty of studies that use 2D materials to fabricate floating-gate transistors. In the prior studies, the 2D materials were mainly used as channel and floating gate materials.⁸⁴^,⁸⁵^,⁸⁶^,⁸⁷^,⁸⁸^,⁸⁹^,⁹⁰^,⁹¹^,⁹²^,⁹³^,⁹⁴^,⁹⁵ Thinner channel materials can achieve a larger memory window and the thinner floating-gate layer will reduce the crosstalk between different cells. However, the programming speed of these 2D floating-gate transistors is limited to the millisecond, far below the speed of volatile memory. The strength of 2D floating-gate transistors is that their band structure can be flexibly designed and the band engineering can be used to regulate the electrical performance of memory devices.⁹⁶ Liu et al.⁹⁷ have developed an attractive semi-floating gate (SFG) memory technology that largely advances the device programming speed to the level of DRAM. Figure 6B shows the structure of 2D SFG memory and there is a WSe₂/MoS₂ p-n-heterojunction has been embedded into the tunneling layer. Utilizing the embedded p-n-junction, the charges of the channel material can flow into the floating gate using relatively small voltage control with an ultrahigh-speed writing operation (−5 V, 15 ns). However, the introduction of the p-n-junction brings about an ultrafast speed but also causes the data retention time (10s) is not long enough because of the charge leakage. Although the retention time can be enhanced by local field modulation (63.5 s)⁹⁸ and much longer than that of DRAM (64 ms), an ultrafast non-volatile floating-gate transistor would be desirable.

In 2021, Wu et al.⁹⁹ and Liu et al.¹⁰⁰ independently published an ultrafast non-volatile floating-gate transistor using vdWs heterostructure. Wu et al. owed the extraordinary programming speed to the atomically sharp interfaces and demonstrated that the data can be stored for at least 5400 s without noteworthy degradation (linear extrapolation: 10 years retention time). Liu et al. have further verified the ultrafast non-volatile characteristics in a high-temperature test (commercial standard retention time test). Besides the strengthening of a suitable barrier height, gate coupling ratio and clean interface, Liu et al. also indicated that the tunneling mechanism of the 2D floating-gate transistor is not the same as the traditional silicon floating-gate transistor. As shown in Figure 6C, the energy bands of the channel can be sharply bent because of ultrathin electrostatic modulation of 2D semiconductors, which forms double barriers to enhance tunneling efficiency. Although the programming speed has dramatically improved, the ultrafast non-volatile transistors are based on high operation voltage and the thickness of the memory stack should be further optimized to cut down the amplitude of the programming.

Conclusion and outlook

Making use of the ultrathin body and the dangling-bond-free surface, 2D materials demonstrate remarkable advantages in size downscaling and heterostructure innovation. The ultrashort gate-length transistor demonstration is far beyond the ability of the planar silicon transistor. The various steep SS transistors and ultrafast floating-gate transistors have significantly broken the performance limitations of silicon transistors. However, the perfect interface also leads to issues on large-scale integration. There is already huge progress in the integration process, because we have discussed in the contact optimization and dielectric integration parts, but the large-scale integration process still needs heavy study. In the following, we will briefly discuss the challenges for the application of the 2D material from lab to fab.

For large-scale integration, wafer-scale growth of 2D materials is essential. For now, there are only a few kinds of 2D materials that can be large-scale grown and accurately controlling the phase and layer number of the 2D materials remains a challenge.¹⁰¹^,¹⁰² A stable and effective doping method of 2D materials is necessary for building energy-efficient complementary circuits but this field is rather slow in progress. The material growth with proper doping is still the key obstacle that hinders the 2D transistor from lab to fab. As for the device fabrication, the contacts and dielectric integration are in the first place to guarantee the performance of integrated circuits. Although the bismuth contacts provide a low enough contact resistance on 2D materials (123Ω μm), similar to the contact resistance in the state-of-the-art silicon transistor, the melting point of bismuth is too small to be compatible with the CMOS process. More semimetal contact schemes with higher temperature tolerance should be explored, such as antimony.¹⁰³ The dielectric integration on 2D materials has challenges to scaling the EOT below 1 nm and the high-κ deposition process will also affect the threshold voltage of channel.¹⁰⁴ The self-oxidized native dielectric can realize EOT to 0.5 nm, but the applicative materials are very limited.

What’s more, a large portion of high-performance 2D transistors is based on the vdWs heterostructure which brings forward great challenges in large-scale integration. The vdWs integration method can allow flexible assemble various heterostructures, but the transfer precision is very poor and it is still no way to improve the precision to that of lithography. To integrate heterostructure devices with high density, selective etching 2D materials¹⁰⁵^,¹⁰⁶^,¹⁰⁷ and self-aligned process⁴⁰^,¹⁰⁸ should be developed.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (62004040), Shanghai Pilot Program for Basic Research - FuDan University 21TQ1400100 (21TQ011), Shanghai Rising-Star Program (22QA1400700), and the young scientist project of MOE innovation platform.

Author contributions

Q.Z., C.L., and P.Z. discussed and wrote the manuscript.

Declaration of interests

The authors declare no competing interests.

Inclusion and diversity

We support inclusive, diverse, and equitable conduct of research.

Contributor Information

Chunsen Liu, Email: chunsen_liu@fudan.edu.cn.

Peng Zhou, Email: pengzhou@fudan.edu.cn.

References

1.Razavieh A., Zeitzoff P., Nowak E.J. Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans. Nanotechnol. 2019;18:999–1004. [Google Scholar]
2.Liu C., Chen H., Wang S., Liu Q., Jiang Y.G., Zhang D.W., Liu M., Zhou P. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 2020;15:545–557. doi: 10.1038/s41565-020-0724-3. [DOI] [PubMed] [Google Scholar]
3.Tao L., Cinquanta E., Chiappe D., Grazianetti C., Fanciulli M., Dubey M., Molle A., Akinwande D. Silicene field-effect transistors operating at room temperature. Nat. Nanotechnol. 2015;10:227–231. doi: 10.1038/nnano.2014.325. [DOI] [PubMed] [Google Scholar]
4.Li X.X., Liu Y., Luo J., Huang Z.D., Zhang C., Fu Y. Van der Waals integration before and beyond two-dimensional materials. Nature. 2019;17:323. doi: 10.1038/s41586-019-1013-x. [DOI] [PubMed] [Google Scholar]
5.Horowitz M. IEEE; 2014. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 10–14. [DOI] [Google Scholar]
6.Lee D.U., Kim K.W., Kim K.W., Kim H., Kim J.Y., Park Y.J., Kim J.H., Kim D.S., Park H.B., Shin J.W. IEEE; 2014. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 432–433. [DOI] [Google Scholar]
7.Liu D., Park S. Three-dimensional and 2.5 dimensional interconnection technology: state of the art. J. Electron. Packag. 2014;136:014001. doi: 10.1115/1.4026615. [DOI] [Google Scholar]
8.Shulaker M.M., Hills G., Park R.S., Howe R.T., Saraswat K., Wong H.S.P., Mitra S. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature. 2017;547:74–78. doi: 10.1038/nature22994. [DOI] [PubMed] [Google Scholar]
9.Liu Y., Weiss N.O., Duan X., Cheng H.-C., Huang Y., Duan X. Van der Waals heterostructures and devices. Nat. Rev. Mater. 2016;1:16042. doi: 10.1038/natrevmats.2016.42. [DOI] [Google Scholar]
10.Chhowalla M., Jena D., Zhang H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 2016;1:16052. doi: 10.1038/natrevmats.2016.52. [DOI] [Google Scholar]
11.Mounet N., Gibertini M., Schwaller P., Campi D., Merkys A., Marrazzo A., Sohier T., Castelli I.E., Cepellotti A., Pizzi G., Marzari N. Two-dimensional materials from high-throughput computational exfoliation of experimentally known compounds. Nat. Nanotechnol. 2018;13:246–252. doi: 10.1038/s41565-017-0035-5. [DOI] [PubMed] [Google Scholar]
12.Liu C., Yan X., Zhang E., Song X., Sun Q., Ding S., Bao W., Xiu F., Zhou P., Zhang D.W. Various and tunable transport properties of WSe2 transistor formed by metal contacts. Small. 2017;13:1604319. doi: 10.1002/smll.201604319. [DOI] [PubMed] [Google Scholar]
13.Wang Z., Xia H., Wang P., Zhou X., Liu C., Zhang Q., Wang F., Huang M., Chen S., Wu P., et al. Controllable doping in 2D layered materials. Adv. Mater. 2021;33:e2104942. doi: 10.1002/adma.202104942. [DOI] [PubMed] [Google Scholar]
14.Wang X., Liu C., Chen Y., Wu G., Yan X., Huang H., Wang P., Tian B., Hong Z., Wang Y., et al. Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels. 2D Mater. 2017;4:025036. doi: 10.1088/2053-1583/aa5c17. [DOI] [Google Scholar]
15.Zhang Z., Wang S., Liu C., Xie R., Hu W., Zhou P. All-in-one two-dimensional retinomorphic hardware device for motion detection and recognition. Nat. Nanotechnol. 2021;17:27–32. doi: 10.1038/s41565-021-01003-1. [DOI] [PubMed] [Google Scholar]
16.Gibertini M., Koperski M., Morpurgo A.F., Novoselov K.S. Magnetic 2D materials and heterostructures. Nat. Nanotechnol. 2019;14:408–419. doi: 10.1038/s41565-019-0438-6. [DOI] [PubMed] [Google Scholar]
17.Fei Z., Zhao W., Palomaki T.A., Sun B., Miller M.K., Zhao Z., Yan J., Xu X., Cobden D.H. Ferroelectric switching of a two-dimensional metal. Nature. 2018;560:336–339. doi: 10.1038/s41586-018-0336-3. [DOI] [PubMed] [Google Scholar]
18.Xue F., He X., Retamal J.R.D., Han A., Zhang J., Liu Z., Huang J.K., Hu W., Tung V., He J.H., et al. Gate-Tunable and multidirection-switchable memristive phenomena in a van der Waals ferroelectric. Adv. Mater. 2019;31:1901300. doi: 10.1002/adma.201901300. [DOI] [PubMed] [Google Scholar]
19.Dennard R.H., Gaensslen F.H., Yu H.-N., Rideout V.L., Bassous E., LeBlanc A.R. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J. Solid State Circ. 1974;9:256–268. doi: 10.1109/jssc.1974.1050511. [DOI] [Google Scholar]
20.Baccarani G., Wordeman M.R., Dennard R.H. Generalized scaling theory and its application to a ¼ micrometer MOSFET design. IEEE Trans. Electron. Dev. 1984;31:452–462. doi: 10.1109/T-ED.1984.21550. [DOI] [Google Scholar]
21.Irisawa T., Numata T., Tezuka T., Sugiyama N., Takagi S.I. IEEE; 2006. In 2006 International Electron Devices Meeting; pp. 1–4. [DOI] [Google Scholar]
22.Uchida K., Watanabe H., Kinoshita A., Koga J., Numata T., Takagi S. IEEE; 2002. In Technical Digest-International Electron Devices Meeting; pp. 47–50. [DOI] [Google Scholar]
23.Zhu W., Perebeinos V., Freitag M., Avouris P. Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene. Phys. Rev. B. 2009;80:235402. doi: 10.1103/physrevb.80.235402. [DOI] [Google Scholar]
24.Banszerus L., Schmitz M., Engels S., Dauber J., Oellers M., Haupt F., Watanabe K., Taniguchi T., Beschoten B., Stampfer C. Ultrahigh-mobility graphene devices from chemical vapor deposition on reusable copper. Sci. Adv. 2015;1:e1500222. doi: 10.1126/sciadv.1500222. [DOI] [PMC free article] [PubMed] [Google Scholar]
25.Li L.F., Chan R.L.Y., Lu L., Shen J., Zhang L., Wu W.K.K., Wang L., Hu T., Li M.X., Cho C.H. Black phosphorus field-effect transistors. Int. J. Mol. Med. 2014;34:372–380. doi: 10.3892/ijmm.2014.1786. [DOI] [PubMed] [Google Scholar]
26.Doganov R.A., O’Farrell E.C.T., Koenig S.P., Yeo Y., Ziletti A., Carvalho A., Campbell D.K., Coker D.F., Watanabe K., Taniguchi T., et al. Transport properties of pristine few-layer black phosphorus by van der Waals passivation in an inert atmosphere. Nat. Commun. 2015;6:6647. doi: 10.1038/ncomms7647. [DOI] [PubMed] [Google Scholar]
27.Lembke D., Allain A., Kis A. Thickness-dependent mobility in two-dimensional MoS2 transistors. Nanoscale. 2015;7:6255–6260. doi: 10.1039/c4nr06331g. [DOI] [PubMed] [Google Scholar]
28.Yu Z., Ong Z.Y., Pan Y., Cui Y., Xin R., Shi Y., Wang B., Wu Y., Chen T., Zhang Y.W., et al. Realization of room-temperature phonon-limited carrier transport in monolayer MoS2 by dielectric and carrier screening. Adv. Mater. 2016;28:547–552. doi: 10.1002/adma.201503033. [DOI] [PubMed] [Google Scholar]
29.Fang H., Chuang S., Chang T.C., Takei K., Takahashi T., Javey A. High-performance single layered WSe2 p-FETs with chemically doped contacts. Nano Lett. 2012;12:3788–3792. doi: 10.1021/nl301702r. [DOI] [PubMed] [Google Scholar]
30.Liu W., Kang J., Sarkar D., Khatami Y., Jena D., Banerjee K. Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. Nano Lett. 2013;13:1983–1990. doi: 10.1021/nl304777e. [DOI] [PubMed] [Google Scholar]
31.Cui Y., Xin R., Yu Z., Pan Y., Ong Z.-Y., Wei X., Wang J., Nan H., Ni Z., Wu Y., et al. High-performance monolayer WS2 field-effect transistors on high-κ dielectrics. Adv. Mater. 2015;27:5230–5234. doi: 10.1002/adma.201502222. [DOI] [PubMed] [Google Scholar]
32.Li K.-S., Wu B.-W., Li L.-J., Li M.-Y., Cheng C.-C.K., Hsu C.-L., Lin C.-H., Chen Y.-J., Chen C.-C., Wu C.-T. IEEE; 2016. MoS 2 U-Shape MOSFET with 10 Nm Channel Length and Poly-Si Source/drain Serving as Seed for Full Wafer CVD MoS 2 Availability; pp. 1–2. [Google Scholar]
33.Ashokbhai Patel K., Grady R.W., Smithe K.K.H., Pop E., Sordan R. Ultra-scaled MoS2 transistors and circuits fabricated without nanolithography. 2D Mater. 2019;7:015018. [Google Scholar]
34.Desai S.B., Madhvapathy S.R., Sachid A.B., Llinas J.P., Wang Q., Ahn G.H., Pitner G., Kim M.J., Bokor J., Hu C., et al. MoS2 transistors with 1-nanometer gate lengths. Science. 2016;354:99–102. doi: 10.1126/science.aah4698. [DOI] [PubMed] [Google Scholar]
35.Jiang J., Doan M.H., Sun L., Kim H., Yu H., Joo M.K., Park S.H., Yang H., Duong D.L., Lee Y.H. Ultrashort vertical-channel van der Waals semiconductor transistors. Adv. Sci. 2020;7:1902964. doi: 10.1002/advs.201902964. [DOI] [PMC free article] [PubMed] [Google Scholar]
36.Wu F., Tian H., Shen Y., Hou Z., Ren J., Gou G., Sun Y., Yang Y., Ren T.-L. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature. 2022;603:259–264. doi: 10.1038/s41586-021-04323-3. [DOI] [PubMed] [Google Scholar]
37.Mertens H., Ritzenthaler R., Hikavyy A., Kim M.S., Tao Z., Wostyn K., Chew S.A., De Keersgieter A., Mannaert G., Rosseel E., et al. 2016 Ieee Symposium Vlsi Technology. 2016. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates; pp. 1–2. [DOI] [Google Scholar]
38.Loubet N., Kal S., Alix C., Pancharatnam S., Zhou H., Durfee C., Belyansky M., Haller N., Watanabe K., Devarajan T., et al. 2019 Ieee Int Electron Devices Meet Iedm. 2019. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices; pp. 11.14.11–11.14.14. [DOI] [Google Scholar]
39.Barraud S., Previtali B., Vizioz C., Hartmann J.M., Sturm J., Lassarre J., Perrot C., Rodriguez P., Loup V., Magalhaes-Lucas A., et al. 2020. 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing. [Google Scholar]
40.Huang X., Yang B., Liu Q., Zhang R., Tang S., Story M., Chen H., Li J., Jiang Y.-G., Zhang D.W., Zhou P. 2020 Ieee Int Electron Devices Meet Iedm. 2020. High drive and low leakage current MBC FET with channel thickness 1.2nm/0.6nm; pp. 12.11.11–12.11.14. [DOI] [Google Scholar]
41.Huang X., Liu C., Zeng S., Tang Z., Wang S., Chen X., Zhang D.W., Zhou P. Ultrathin multibridge channel transistor enabled by van der Waals assembly. Adv. Mater. 2021;33:e2102201. doi: 10.1002/adma.202102201. [DOI] [PubMed] [Google Scholar]
42.Samavedam S., Ryckaert J., Beyne E., Ronse K., Horiguchi N., Tokei Z., Radu I., Bardon M., Na M., Spessot A. IEEE; 2020. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips; pp. 1.1.1–1.1.10. [Google Scholar]
43.Resta G.V., Balaji Y., Lin D., Radu I.P., Catthoor F., Gaillardon P.E., De Micheli G. Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors. ACS Nano. 2018;12:7039–7047. doi: 10.1021/acsnano.8b02739. [DOI] [PubMed] [Google Scholar]
44.Yi J., Sun X., Zhu C., Li S., Liu Y., Zhu X., You W., Liang D., Shuai Q., Wu Y., et al. Double-gate MoS2 field-effect transistors with full-range tunable threshold voltage for multifunctional logic circuits. Adv. Mater. 2021;33:e2101036. doi: 10.1002/adma.202101036. [DOI] [PubMed] [Google Scholar]
45.Wu P., Reis D., Hu X.S., Appenzeller J. Two-dimensional transistors with reconfigurable polarities for secure circuits. Nat. Electron. 2020;4:45–53. doi: 10.1038/s41928-020-00511-7. [DOI] [Google Scholar]
46.Pan C., Wang C.-Y., Liang S.-J., Wang Y., Cao T., Wang P., Wang C., Wang S., Cheng B., Gao A., et al. Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions. Nat. Electron. 2020;3:383–390. doi: 10.1038/s41928-020-0433-9. [DOI] [Google Scholar]
47.Liu C., Chen H., Hou X., Zhang H., Han J., Jiang Y.-G., Zeng X., Zhang D.W., Zhou P. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat. Nanotechnol. 2019;14:662–667. doi: 10.1038/s41565-019-0462-6. [DOI] [PubMed] [Google Scholar]
48.Zeng S., Liu C., Huang X., Tang Z., Liu L., Zhou P. An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions. Nat. Commun. 2022;13:56. doi: 10.1038/s41467-021-27644-3. [DOI] [PMC free article] [PubMed] [Google Scholar]
49.Xiong Y., Chen X., Zhang Z., Chen H., Li J., Liu C., Zhou P. Temperature-Dependent logic behavior of logic transistors based on WS2. IEEE Access. 2020;8:79368–79375. doi: 10.1109/access.2020.2990437. [DOI] [Google Scholar]
50.Chen X., Gu L., Liu L., Chen H., Li J., Liu C., Zhou P. Temperature-switching logic in MoS 2 single transistors. Chin. Phys. B. 2020;29:097201. doi: 10.1088/1674-1056/aba9cf. [DOI] [Google Scholar]
51.Fang H., Chuang S., Chang T.C., Takei K., Takahashi T., Javey A. High-performance single layered WSe 2 p-FETs with chemically doped contacts. Nano Lett. 2012;12:3788–3792. doi: 10.1021/nl301702r. [DOI] [PubMed] [Google Scholar]
52.Lei S., Wang X., Li B., Kang J., He Y., George A., Ge L., Gong Y., Dong P., Jin Z., et al. Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry. Nat. Nanotechnol. 2016;11:465–471. doi: 10.1038/nnano.2015.323. [DOI] [PubMed] [Google Scholar]
53.Zhang X., Liao Q., Liu S., Kang Z., Zhang Z., Du J., Li F., Zhang S., Xiao J., Liu B., et al. Poly(4-styrenesulfonate)-induced sulfur vacancy self-healing strategy for monolayer MoS2 homojunction photodiode. Nat. Commun. 2017;8:15881. doi: 10.1038/ncomms15881. [DOI] [PMC free article] [PubMed] [Google Scholar]
54.Gong Y., Yuan H., Wu C.-L., Tang P., Yang S.-Z., Yang A., Li G., Liu B., van de Groep J., Brongersma M.L., et al. Spatially controlled doping of two-dimensional SnS2 through intercalation for electronics. Nat. Nanotechnol. 2018;13:294–299. doi: 10.1038/s41565-018-0069-3. [DOI] [PubMed] [Google Scholar]
55.Kang J., Liu W., Sarkar D., Jena D., Banerjee K. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors. Phys. Rev. X. 2014;4:031005. doi: 10.1103/PhysRevX.4.031005. [DOI] [Google Scholar]
56.Allain A., Kang J., Banerjee K., Kis A. Electrical contacts to two-dimensional semiconductors. Nat. Mater. 2015;14:1195–1205. doi: 10.1038/nmat4452. [DOI] [PubMed] [Google Scholar]
57.Das S., Chen H.-Y., Penumatcha A.V., Appenzeller J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 2013;13:100–105. doi: 10.1021/nl303583v. [DOI] [PubMed] [Google Scholar]
58.Liu W., Kang J., Sarkar D., Khatami Y., Jena D., Banerjee K. Role of metal contacts in designing high-performance monolayer n-type WSe 2 field effect transistors. Nano Lett. 2013;13:1983–1990. doi: 10.1021/nl304777e. [DOI] [PubMed] [Google Scholar]
59.Chuang S., Battaglia C., Azcatl A., McDonnell S., Kang J.S., Yin X., Tosun M., Kapadia R., Fang H., Wallace R.M., Javey A. MoS2 P-type transistors and diodes enabled by high work function MoOx contacts. Nano Lett. 2014;14:1337–1342. doi: 10.1021/nl4043505. [DOI] [PubMed] [Google Scholar]
60.Liu Y., Guo J., Zhu E., Liao L., Lee S.-J., Ding M., Shakir I., Gambin V., Huang Y., Duan X. Approaching the Schottky–Mott limit in van der Waals metal–semiconductor junctions. Nature. 2018;557:696–700. doi: 10.1038/s41586-018-0129-8. [DOI] [PubMed] [Google Scholar]
61.Kwon G., Choi Y.-H., Lee H., Kim H.-S., Jeong J., Jeong K., Baik M., Kwon H., Ahn J., Lee E., Cho M.-H. Interaction- and defect-free van der Waals contacts between metals and two-dimensional semiconductors. Nat. Electron. 2022;5:241–247. doi: 10.1038/s41928-022-00746-6. [DOI] [Google Scholar]
62.Shen P.C., Su C., Lin Y., Chou A.S., Cheng C.C., Park J.H., Chiu M.H., Lu A.Y., Tang H.L., Tavakoli M.M., et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature. 2021;593:211–217. doi: 10.1038/s41586-021-03472-9. [DOI] [PubMed] [Google Scholar]
63.Li W., Fan D., Shao L., Huang F., Liang L., Li T., Xu Y., Tu X., Wang P., Yu Z. IEEE; 2021. High-performance CVD MoS 2 Transistors with Self-Aligned Top-Gate and Bi Contact; pp. 37.33.31–37.33.34. [Google Scholar]
64.Lin Y., Shen P.C., Su C., Chou A.S., Wu T., Cheng C.C., Park J.H., Chiu M.H., Lu A.Y., Tang H.L., et al. Contact engineering for high-performance N-type 2D semiconductor transistors. 2021;11:37.32.31–37.32.34. [Google Scholar]
65.Wang L., Meric I., Huang P.Y., Gao Q., Gao Y., Tran H., Taniguchi T., Watanabe K., Campos L.M., Muller D.A., et al. One-dimensional electrical contact to a two-dimensional material. Science. 2013;342:614–617. doi: 10.1126/science.1244358. [DOI] [PubMed] [Google Scholar]
66.Xiao J., Kang Z., Liu B., Zhang X., Du J., Chen K., Yu H., Liao Q., Zhang Z., Zhang Y. Record-high saturation current in end-bond contacted monolayer MoS2 transistors. Nano Res. 2022;15:475–481. doi: 10.1007/s12274-021-3504-y. [DOI] [Google Scholar]
67.Yang W., Sun Q.-Q., Geng Y., Chen L., Zhou P., Ding S.-J., Zhang D.W. The integration of sub-10 nm gate oxide on MoS2 with ultra low leakage and enhanced mobility. Sci. Rep. 2015;5:11921. doi: 10.1038/srep11921. [DOI] [PMC free article] [PubMed] [Google Scholar]
68.Zou X., Wang J., Chiu C.H., Wu Y., Xiao X., Jiang C., Wu W.W., Mai L., Chen T., Li J., et al. Interface engineering for high-performance top-gated MoS2 field-effect transistors. Adv. Mater. 2014;26:6255–6261. doi: 10.1002/adma.201402008. [DOI] [PubMed] [Google Scholar]
69.Hollander M.J., LaBella M., Hughes Z.R., Zhu M., Trumbull K.A., Cavalero R., Snyder D.W., Wang X., Hwang E., Datta S., Robinson J.A. Enhanced transport and transistor performance with oxide seeded high-κ gate dielectrics on wafer-scale epitaxial graphene. Nano Lett. 2011;11:3601–3607. doi: 10.1021/nl201358y. [DOI] [PubMed] [Google Scholar]
70.Li W., Zhou J., Cai S., Yu Z., Zhang J., Fang N., Li T., Wu Y., Chen T., Xie X., et al. Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices. Nat. Electron. 2019;2:563–571. [Google Scholar]
71.Li T., Tu T., Sun Y., Fu H., Yu J., Xing L., Wang Z., Wang H., Jia R., Wu J., et al. A native oxide high-κ gate dielectric for two-dimensional electronics. Nat. Electron. 2020;3:473–478. doi: 10.1038/s41928-020-0444-6. [DOI] [Google Scholar]
72.Zhang Y., Yu J., Zhu R., Wang M., Tan C., Tu T., Zhou X., Zhang C., Yu M., Gao X., et al. A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm. Nat. Electron. 2022;5:643–649. [Google Scholar]
73.Seabaugh A.C., Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE. 2010;98:2095–2110. doi: 10.1109/jproc.2010.2070470. [DOI] [Google Scholar]
74.Ionescu A.M., Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature. 2011;479:329–337. doi: 10.1038/nature10679. [DOI] [PubMed] [Google Scholar]
75.Khan A.I., Yeung C.W., Chenming H., Salahuddin S. IEEE; 2011. In 2011 International Electron Devices Meeting; pp. 11.13.11–11.13.14. [DOI] [Google Scholar]
76.Kim S., Myeong G., Shin W., Lim H., Kim B., Jin T., Chang S., Watanabe K., Taniguchi T., Cho S. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nat. Nanotechnol. 2020;15:203–206. doi: 10.1038/s41565-019-0623-7. [DOI] [PubMed] [Google Scholar]
77.Si M., Su C.J., Jiang C., Conrad N.J., Zhou H., Maize K.D., Qiu G., Wu C.T., Shakouri A., Alam M.A., Ye P.D. Steep-slope hysteresis-free negative-capacitance 2D transistors. Nat. Nanotechnol. 2018;13:24–28. doi: 10.1038/s41565-017-0010-1. [DOI] [PubMed] [Google Scholar]
78.Yu Z., Wang H., Li W., Xu S., Song X., Wang S., Wang P., Zhou P., Shi Y., Chai Y. IEEE; 2004. In 2017 IEEE International Electron Devices Meeting (IEDM) pp. 23.26.21–23.26.24. [Google Scholar]
79.Si M., Jiang C., Chung W., Du Y., Alam M.A., Ye P.D. Steep-slope WSe2 negative capacitance field-effect transistor. Nano Lett. 2018;18:3682–3687. doi: 10.1021/acs.nanolett.8b00816. [DOI] [PubMed] [Google Scholar]
80.Xiong X., Huang M., Hu B., Li X., Liu F., Li S., Tian M., Li T., Song J., Wu Y. A transverse tunnelling field-effect transistor made from a van der Waals heterostructure. Nat. Electron. 2020;3:106–112. [Google Scholar]
81.Qiu C., Liu F., Xu L., Deng B., Xiao M., Si J., Lin L., Zhang Z., Wang J., Guo H., et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science. 2018;361:387–392. doi: 10.1126/science.aap9195. [DOI] [PubMed] [Google Scholar]
82.Tang Z., Liu C., Huang X., Zeng S., Liu L., Li J., Jiang Y.G., Zhang D.W., Zhou P. A steep-slope MoS2/graphene Dirac-source field-effect transistor with a large drive current. Nano Lett. 2021;21:1758–1764. doi: 10.1021/acs.nanolett.0c04657. [DOI] [PubMed] [Google Scholar]
83.Yang J.J., Strukov D.B., Stewart D.R. Memristive devices for computing. Nat. Nanotechnol. 2013;8:13–24. doi: 10.1038/nnano.2012.240. [DOI] [PubMed] [Google Scholar]
84.Choi M.S., Lee G.-H., Yu Y.-J., Lee D.-Y., Lee S.H., Kim P., Hone J., Yoo W.J. Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices. Nat. Commun. 2013;4:1624. doi: 10.1038/ncomms2652. [DOI] [PubMed] [Google Scholar]
85.Ning Z., Olmedo M., Wang G., Liu J. Graphene based nickel nanocrystal flash memory. Appl. Phys. Lett. 2011;99:223312. [Google Scholar]
86.Hou X., Yan X., Liu C., Ding S., Zhang D.W., Zhou P. Operation mode switchable charge-trap memory based on few-layer MoS2. Semicond. Sci. Technol. 2018;33:034001. doi: 10.1088/1361-6641/aaa79e. [DOI] [Google Scholar]
87.Liu C., Yan X., Wang J., Ding S., Zhou P., Zhang D.W. Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2. Small. 2017;13:1604128. doi: 10.1002/smll.201604128. [DOI] [PubMed] [Google Scholar]
88.Chen M., Nam H., Wi S., Priessnitz G., Gunawan I.M., Liang X. Multibit data storage states formed in plasma-treated MoS transistors. ACS Nano. 2014;8:4023–4032. doi: 10.1021/nn501181t. [DOI] [PubMed] [Google Scholar]
89.Zhang E., Wang W., Zhang C., Jin Y., Zhu G., Sun Q., Zhang D.W., Zhou P., Xiu F. Tunable charge-trap memory based on few-layer MoS2. ACS Nano. 2015;9:612–619. doi: 10.1021/nn5059419. [DOI] [PubMed] [Google Scholar]
90.Mishra A., Kalita H., Waikar M., Gour A., Aslam M. 2012. Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory. [Google Scholar]
91.Bertolazzi S., Krasnozhon D., Kis A. Nonvolatile memory cells based on MoS2/graphene heterostructures. ACS Nano. 2013;7:3246–3252. doi: 10.1021/nn3059136. [DOI] [PubMed] [Google Scholar]
92.Li D., Chen M., Sun Z., Yu P., Liu Z., Ajayan P.M., Zhang Z. Two-dimensional non-volatile programmable p–n junctions. Nat. Nanotechnol. 2017;12:901–906. doi: 10.1038/nnano.2017.104. [DOI] [PubMed] [Google Scholar]
93.Zhang P., Li D., Chen M., Zong Q., Shen J., Wan D., Zhu J., Zhang Z. Floating-gate controlled programmable non-volatile black phosphorus PNP junction memory. Nanoscale. 2018;10:3148–3152. doi: 10.1039/c7nr08515j. [DOI] [PubMed] [Google Scholar]
94.Vu Q.A., Shin Y.S., Kim Y.R., Nguyen V.L., Kang W.T., Kim H., Luong D.H., Lee I.M., Lee K., Ko D.S., et al. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio. Nat. Commun. 2016;7:12725. doi: 10.1038/ncomms12725. [DOI] [PMC free article] [PubMed] [Google Scholar]
95.Vu Q.A., Kim H., Nguyen V.L., Won U.Y., Adhikari S., Kim K., Lee Y.H., Yu W.J. A high-on/off-ratio floating-gate memristor array on a flexible substrate via CVD-grown large-area 2D layer stacking. Adv. Mater. 2017;29:1703363–1703367. doi: 10.1002/adma.201703363. [DOI] [PubMed] [Google Scholar]
96.Liu C., Yan X., Wang J., Ding S., Zhou P., Zhang D.W. Eliminating overerase behavior by designing energy band in high-speed charge-trap memory based on WSe2. Small. 2017;13:1604128. doi: 10.1002/smll.201604128. [DOI] [PubMed] [Google Scholar]
97.Liu C., Yan X., Song X., Ding S., Zhang D.W., Zhou P. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications. Nat. Nanotechnol. 2018;13:404–410. doi: 10.1038/s41565-018-0102-6. [DOI] [PubMed] [Google Scholar]
98.Ding Y., Liu L., Li J., Cao R., Jiang Y.G., Liu C., Liu Q., Zhou P. A semi-floating memory with 535% enhancement of refresh time by local field modulation. Adv. Funct. Mater. 2020;30:1908089. doi: 10.1002/adfm.201908089. [DOI] [Google Scholar]
99.Wu L., Wang A., Shi J., Yan J., Zhou Z., Bian C., Ma J., Ma R., Liu H., Chen J., et al. Atomically sharp interface enabled ultrahigh-speed non-volatile memory devices. Nat. Nanotechnol. 2021;16:882–887. doi: 10.1038/s41565-021-00904-5. [DOI] [PubMed] [Google Scholar]
100.Liu L., Liu C., Jiang L., Li J., Ding Y., Wang S., Jiang Y.G., Sun Y.B., Wang J., Chen S., et al. Ultrafast non-volatile flash memory based on van der Waals heterostructures. Nat. Nanotechnol. 2021;16:874–881. doi: 10.1038/s41565-021-00921-4. [DOI] [PubMed] [Google Scholar]
101.Dorow C.J., O’Brien K.P., Naylor C.H., Lee S., Penumatcha A., Hsiao A., Tronic T., Christenson M., Maxey K., Zhu H., et al. Vol. 13. 2021. pp. 1–2. (Advancing monolayer 2D NMOS and PMOS transistor integration from growth to van der Waals interface engineering for ultimate CMOS scaling). [Google Scholar]
102.Li X., Cai W., An J., Kim S., Nah J., Yang D., Piner R., Velamakanni A., Jung I., Tutuc E., et al. Large-area synthesis of high-quality and uniform graphene films on copper foils. Science. 2009;324:1312–1314. doi: 10.1126/science.1171245. [DOI] [PubMed] [Google Scholar]
103.Chou A.S., Wu T., Cheng C.C., Zhan S.S., Ni I.C., Wang S.Y., Chang Y.C., Liew S.L., Chen E., Chang W.H., et al. Vol. 11. 2021. pp. 7.2.1–7.2.4. (Antimony semimetal contact with enhanced thermal stability for high performance 2D electronics). [Google Scholar]
104.Das S., Chen H.-Y., Penumatcha A.V., Appenzeller J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 2013;13:100–105. doi: 10.1021/nl303583v. [DOI] [PubMed] [Google Scholar]
105.Xie L., Jiao L., Dai H. Selective etching of graphene edges by hydrogen plasma. J. Am. Chem. Soc. 2010;132:14751–14753. doi: 10.1021/ja107071g. [DOI] [PubMed] [Google Scholar]
106.Ryu G.H., Zhu T., Chen J., Sinha S., Shautsova V., Grossman J.C., Warner J.H. Striated 2D lattice with sub-nm 1D etch channels by controlled thermally induced phase transformations of PdSe2. Adv. Mater. 2019;31:1904251. doi: 10.1002/adma.201904251. [DOI] [PubMed] [Google Scholar]
107.Zhou J., Zhang C., Shi L., Chen X., Kim T.S., Gyeon M., Chen J., Wang J., Yu L., Wang X., et al. Non-invasive digital etching of van der Waals semiconductors. Nat. Commun. 2022;13:1844–1848. doi: 10.1038/s41467-022-29447-6. [DOI] [PMC free article] [PubMed] [Google Scholar]
108.Liao L., Lin Y.-C., Bao M., Cheng R., Bai J., Liu Y., Qu Y., Wang K.L., Huang Y., Duan X. High-speed graphene transistors with a self-aligned nanowire gate. Nature. 2010;467:305–308. doi: 10.1038/nature09405. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib1] 1.Razavieh A., Zeitzoff P., Nowak E.J. Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans. Nanotechnol. 2019;18:999–1004. [Google Scholar]

[bib2] 2.Liu C., Chen H., Wang S., Liu Q., Jiang Y.G., Zhang D.W., Liu M., Zhou P. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 2020;15:545–557. doi: 10.1038/s41565-020-0724-3. [DOI] [PubMed] [Google Scholar]

[bib3] 3.Tao L., Cinquanta E., Chiappe D., Grazianetti C., Fanciulli M., Dubey M., Molle A., Akinwande D. Silicene field-effect transistors operating at room temperature. Nat. Nanotechnol. 2015;10:227–231. doi: 10.1038/nnano.2014.325. [DOI] [PubMed] [Google Scholar]

[bib4] 4.Li X.X., Liu Y., Luo J., Huang Z.D., Zhang C., Fu Y. Van der Waals integration before and beyond two-dimensional materials. Nature. 2019;17:323. doi: 10.1038/s41586-019-1013-x. [DOI] [PubMed] [Google Scholar]

[bib5] 5.Horowitz M. IEEE; 2014. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 10–14. [DOI] [Google Scholar]

[bib6] 6.Lee D.U., Kim K.W., Kim K.W., Kim H., Kim J.Y., Park Y.J., Kim J.H., Kim D.S., Park H.B., Shin J.W. IEEE; 2014. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 432–433. [DOI] [Google Scholar]

[bib7] 7.Liu D., Park S. Three-dimensional and 2.5 dimensional interconnection technology: state of the art. J. Electron. Packag. 2014;136:014001. doi: 10.1115/1.4026615. [DOI] [Google Scholar]

[bib8] 8.Shulaker M.M., Hills G., Park R.S., Howe R.T., Saraswat K., Wong H.S.P., Mitra S. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature. 2017;547:74–78. doi: 10.1038/nature22994. [DOI] [PubMed] [Google Scholar]

[bib9] 9.Liu Y., Weiss N.O., Duan X., Cheng H.-C., Huang Y., Duan X. Van der Waals heterostructures and devices. Nat. Rev. Mater. 2016;1:16042. doi: 10.1038/natrevmats.2016.42. [DOI] [Google Scholar]

[bib10] 10.Chhowalla M., Jena D., Zhang H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 2016;1:16052. doi: 10.1038/natrevmats.2016.52. [DOI] [Google Scholar]

[bib11] 11.Mounet N., Gibertini M., Schwaller P., Campi D., Merkys A., Marrazzo A., Sohier T., Castelli I.E., Cepellotti A., Pizzi G., Marzari N. Two-dimensional materials from high-throughput computational exfoliation of experimentally known compounds. Nat. Nanotechnol. 2018;13:246–252. doi: 10.1038/s41565-017-0035-5. [DOI] [PubMed] [Google Scholar]

[bib12] 12.Liu C., Yan X., Zhang E., Song X., Sun Q., Ding S., Bao W., Xiu F., Zhou P., Zhang D.W. Various and tunable transport properties of WSe2 transistor formed by metal contacts. Small. 2017;13:1604319. doi: 10.1002/smll.201604319. [DOI] [PubMed] [Google Scholar]

[bib13] 13.Wang Z., Xia H., Wang P., Zhou X., Liu C., Zhang Q., Wang F., Huang M., Chen S., Wu P., et al. Controllable doping in 2D layered materials. Adv. Mater. 2021;33:e2104942. doi: 10.1002/adma.202104942. [DOI] [PubMed] [Google Scholar]

[bib14] 14.Wang X., Liu C., Chen Y., Wu G., Yan X., Huang H., Wang P., Tian B., Hong Z., Wang Y., et al. Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels. 2D Mater. 2017;4:025036. doi: 10.1088/2053-1583/aa5c17. [DOI] [Google Scholar]

[bib15] 15.Zhang Z., Wang S., Liu C., Xie R., Hu W., Zhou P. All-in-one two-dimensional retinomorphic hardware device for motion detection and recognition. Nat. Nanotechnol. 2021;17:27–32. doi: 10.1038/s41565-021-01003-1. [DOI] [PubMed] [Google Scholar]

[bib16] 16.Gibertini M., Koperski M., Morpurgo A.F., Novoselov K.S. Magnetic 2D materials and heterostructures. Nat. Nanotechnol. 2019;14:408–419. doi: 10.1038/s41565-019-0438-6. [DOI] [PubMed] [Google Scholar]

[bib17] 17.Fei Z., Zhao W., Palomaki T.A., Sun B., Miller M.K., Zhao Z., Yan J., Xu X., Cobden D.H. Ferroelectric switching of a two-dimensional metal. Nature. 2018;560:336–339. doi: 10.1038/s41586-018-0336-3. [DOI] [PubMed] [Google Scholar]

[bib18] 18.Xue F., He X., Retamal J.R.D., Han A., Zhang J., Liu Z., Huang J.K., Hu W., Tung V., He J.H., et al. Gate-Tunable and multidirection-switchable memristive phenomena in a van der Waals ferroelectric. Adv. Mater. 2019;31:1901300. doi: 10.1002/adma.201901300. [DOI] [PubMed] [Google Scholar]

[bib19] 19.Dennard R.H., Gaensslen F.H., Yu H.-N., Rideout V.L., Bassous E., LeBlanc A.R. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J. Solid State Circ. 1974;9:256–268. doi: 10.1109/jssc.1974.1050511. [DOI] [Google Scholar]

[bib20] 20.Baccarani G., Wordeman M.R., Dennard R.H. Generalized scaling theory and its application to a ¼ micrometer MOSFET design. IEEE Trans. Electron. Dev. 1984;31:452–462. doi: 10.1109/T-ED.1984.21550. [DOI] [Google Scholar]

[bib21] 21.Irisawa T., Numata T., Tezuka T., Sugiyama N., Takagi S.I. IEEE; 2006. In 2006 International Electron Devices Meeting; pp. 1–4. [DOI] [Google Scholar]

[bib22] 22.Uchida K., Watanabe H., Kinoshita A., Koga J., Numata T., Takagi S. IEEE; 2002. In Technical Digest-International Electron Devices Meeting; pp. 47–50. [DOI] [Google Scholar]

[bib23] 23.Zhu W., Perebeinos V., Freitag M., Avouris P. Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene. Phys. Rev. B. 2009;80:235402. doi: 10.1103/physrevb.80.235402. [DOI] [Google Scholar]

[bib24] 24.Banszerus L., Schmitz M., Engels S., Dauber J., Oellers M., Haupt F., Watanabe K., Taniguchi T., Beschoten B., Stampfer C. Ultrahigh-mobility graphene devices from chemical vapor deposition on reusable copper. Sci. Adv. 2015;1:e1500222. doi: 10.1126/sciadv.1500222. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib25] 25.Li L.F., Chan R.L.Y., Lu L., Shen J., Zhang L., Wu W.K.K., Wang L., Hu T., Li M.X., Cho C.H. Black phosphorus field-effect transistors. Int. J. Mol. Med. 2014;34:372–380. doi: 10.3892/ijmm.2014.1786. [DOI] [PubMed] [Google Scholar]

[bib26] 26.Doganov R.A., O’Farrell E.C.T., Koenig S.P., Yeo Y., Ziletti A., Carvalho A., Campbell D.K., Coker D.F., Watanabe K., Taniguchi T., et al. Transport properties of pristine few-layer black phosphorus by van der Waals passivation in an inert atmosphere. Nat. Commun. 2015;6:6647. doi: 10.1038/ncomms7647. [DOI] [PubMed] [Google Scholar]

[bib27] 27.Lembke D., Allain A., Kis A. Thickness-dependent mobility in two-dimensional MoS2 transistors. Nanoscale. 2015;7:6255–6260. doi: 10.1039/c4nr06331g. [DOI] [PubMed] [Google Scholar]

[bib28] 28.Yu Z., Ong Z.Y., Pan Y., Cui Y., Xin R., Shi Y., Wang B., Wu Y., Chen T., Zhang Y.W., et al. Realization of room-temperature phonon-limited carrier transport in monolayer MoS2 by dielectric and carrier screening. Adv. Mater. 2016;28:547–552. doi: 10.1002/adma.201503033. [DOI] [PubMed] [Google Scholar]

[bib29] 29.Fang H., Chuang S., Chang T.C., Takei K., Takahashi T., Javey A. High-performance single layered WSe2 p-FETs with chemically doped contacts. Nano Lett. 2012;12:3788–3792. doi: 10.1021/nl301702r. [DOI] [PubMed] [Google Scholar]

[bib30] 30.Liu W., Kang J., Sarkar D., Khatami Y., Jena D., Banerjee K. Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. Nano Lett. 2013;13:1983–1990. doi: 10.1021/nl304777e. [DOI] [PubMed] [Google Scholar]

[bib31] 31.Cui Y., Xin R., Yu Z., Pan Y., Ong Z.-Y., Wei X., Wang J., Nan H., Ni Z., Wu Y., et al. High-performance monolayer WS2 field-effect transistors on high-κ dielectrics. Adv. Mater. 2015;27:5230–5234. doi: 10.1002/adma.201502222. [DOI] [PubMed] [Google Scholar]

[bib32] 32.Li K.-S., Wu B.-W., Li L.-J., Li M.-Y., Cheng C.-C.K., Hsu C.-L., Lin C.-H., Chen Y.-J., Chen C.-C., Wu C.-T. IEEE; 2016. MoS 2 U-Shape MOSFET with 10 Nm Channel Length and Poly-Si Source/drain Serving as Seed for Full Wafer CVD MoS 2 Availability; pp. 1–2. [Google Scholar]

[bib33] 33.Ashokbhai Patel K., Grady R.W., Smithe K.K.H., Pop E., Sordan R. Ultra-scaled MoS2 transistors and circuits fabricated without nanolithography. 2D Mater. 2019;7:015018. [Google Scholar]

[bib34] 34.Desai S.B., Madhvapathy S.R., Sachid A.B., Llinas J.P., Wang Q., Ahn G.H., Pitner G., Kim M.J., Bokor J., Hu C., et al. MoS2 transistors with 1-nanometer gate lengths. Science. 2016;354:99–102. doi: 10.1126/science.aah4698. [DOI] [PubMed] [Google Scholar]

[bib35] 35.Jiang J., Doan M.H., Sun L., Kim H., Yu H., Joo M.K., Park S.H., Yang H., Duong D.L., Lee Y.H. Ultrashort vertical-channel van der Waals semiconductor transistors. Adv. Sci. 2020;7:1902964. doi: 10.1002/advs.201902964. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib36] 36.Wu F., Tian H., Shen Y., Hou Z., Ren J., Gou G., Sun Y., Yang Y., Ren T.-L. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature. 2022;603:259–264. doi: 10.1038/s41586-021-04323-3. [DOI] [PubMed] [Google Scholar]

[bib37] 37.Mertens H., Ritzenthaler R., Hikavyy A., Kim M.S., Tao Z., Wostyn K., Chew S.A., De Keersgieter A., Mannaert G., Rosseel E., et al. 2016 Ieee Symposium Vlsi Technology. 2016. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates; pp. 1–2. [DOI] [Google Scholar]

[bib38] 38.Loubet N., Kal S., Alix C., Pancharatnam S., Zhou H., Durfee C., Belyansky M., Haller N., Watanabe K., Devarajan T., et al. 2019 Ieee Int Electron Devices Meet Iedm. 2019. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices; pp. 11.14.11–11.14.14. [DOI] [Google Scholar]

[bib39] 39.Barraud S., Previtali B., Vizioz C., Hartmann J.M., Sturm J., Lassarre J., Perrot C., Rodriguez P., Loup V., Magalhaes-Lucas A., et al. 2020. 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing. [Google Scholar]

[bib40] 40.Huang X., Yang B., Liu Q., Zhang R., Tang S., Story M., Chen H., Li J., Jiang Y.-G., Zhang D.W., Zhou P. 2020 Ieee Int Electron Devices Meet Iedm. 2020. High drive and low leakage current MBC FET with channel thickness 1.2nm/0.6nm; pp. 12.11.11–12.11.14. [DOI] [Google Scholar]

[bib41] 41.Huang X., Liu C., Zeng S., Tang Z., Wang S., Chen X., Zhang D.W., Zhou P. Ultrathin multibridge channel transistor enabled by van der Waals assembly. Adv. Mater. 2021;33:e2102201. doi: 10.1002/adma.202102201. [DOI] [PubMed] [Google Scholar]

[bib42] 42.Samavedam S., Ryckaert J., Beyne E., Ronse K., Horiguchi N., Tokei Z., Radu I., Bardon M., Na M., Spessot A. IEEE; 2020. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips; pp. 1.1.1–1.1.10. [Google Scholar]

[bib43] 43.Resta G.V., Balaji Y., Lin D., Radu I.P., Catthoor F., Gaillardon P.E., De Micheli G. Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors. ACS Nano. 2018;12:7039–7047. doi: 10.1021/acsnano.8b02739. [DOI] [PubMed] [Google Scholar]

[bib44] 44.Yi J., Sun X., Zhu C., Li S., Liu Y., Zhu X., You W., Liang D., Shuai Q., Wu Y., et al. Double-gate MoS2 field-effect transistors with full-range tunable threshold voltage for multifunctional logic circuits. Adv. Mater. 2021;33:e2101036. doi: 10.1002/adma.202101036. [DOI] [PubMed] [Google Scholar]

[bib45] 45.Wu P., Reis D., Hu X.S., Appenzeller J. Two-dimensional transistors with reconfigurable polarities for secure circuits. Nat. Electron. 2020;4:45–53. doi: 10.1038/s41928-020-00511-7. [DOI] [Google Scholar]

[bib46] 46.Pan C., Wang C.-Y., Liang S.-J., Wang Y., Cao T., Wang P., Wang C., Wang S., Cheng B., Gao A., et al. Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions. Nat. Electron. 2020;3:383–390. doi: 10.1038/s41928-020-0433-9. [DOI] [Google Scholar]

[bib47] 47.Liu C., Chen H., Hou X., Zhang H., Han J., Jiang Y.-G., Zeng X., Zhang D.W., Zhou P. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat. Nanotechnol. 2019;14:662–667. doi: 10.1038/s41565-019-0462-6. [DOI] [PubMed] [Google Scholar]

[bib48] 48.Zeng S., Liu C., Huang X., Tang Z., Liu L., Zhou P. An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions. Nat. Commun. 2022;13:56. doi: 10.1038/s41467-021-27644-3. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib49] 49.Xiong Y., Chen X., Zhang Z., Chen H., Li J., Liu C., Zhou P. Temperature-Dependent logic behavior of logic transistors based on WS2. IEEE Access. 2020;8:79368–79375. doi: 10.1109/access.2020.2990437. [DOI] [Google Scholar]

[bib50] 50.Chen X., Gu L., Liu L., Chen H., Li J., Liu C., Zhou P. Temperature-switching logic in MoS 2 single transistors. Chin. Phys. B. 2020;29:097201. doi: 10.1088/1674-1056/aba9cf. [DOI] [Google Scholar]

[bib51] 51.Fang H., Chuang S., Chang T.C., Takei K., Takahashi T., Javey A. High-performance single layered WSe 2 p-FETs with chemically doped contacts. Nano Lett. 2012;12:3788–3792. doi: 10.1021/nl301702r. [DOI] [PubMed] [Google Scholar]

[bib52] 52.Lei S., Wang X., Li B., Kang J., He Y., George A., Ge L., Gong Y., Dong P., Jin Z., et al. Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry. Nat. Nanotechnol. 2016;11:465–471. doi: 10.1038/nnano.2015.323. [DOI] [PubMed] [Google Scholar]

[bib53] 53.Zhang X., Liao Q., Liu S., Kang Z., Zhang Z., Du J., Li F., Zhang S., Xiao J., Liu B., et al. Poly(4-styrenesulfonate)-induced sulfur vacancy self-healing strategy for monolayer MoS2 homojunction photodiode. Nat. Commun. 2017;8:15881. doi: 10.1038/ncomms15881. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib54] 54.Gong Y., Yuan H., Wu C.-L., Tang P., Yang S.-Z., Yang A., Li G., Liu B., van de Groep J., Brongersma M.L., et al. Spatially controlled doping of two-dimensional SnS2 through intercalation for electronics. Nat. Nanotechnol. 2018;13:294–299. doi: 10.1038/s41565-018-0069-3. [DOI] [PubMed] [Google Scholar]

[bib55] 55.Kang J., Liu W., Sarkar D., Jena D., Banerjee K. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors. Phys. Rev. X. 2014;4:031005. doi: 10.1103/PhysRevX.4.031005. [DOI] [Google Scholar]

[bib56] 56.Allain A., Kang J., Banerjee K., Kis A. Electrical contacts to two-dimensional semiconductors. Nat. Mater. 2015;14:1195–1205. doi: 10.1038/nmat4452. [DOI] [PubMed] [Google Scholar]

[bib57] 57.Das S., Chen H.-Y., Penumatcha A.V., Appenzeller J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 2013;13:100–105. doi: 10.1021/nl303583v. [DOI] [PubMed] [Google Scholar]

[bib58] 58.Liu W., Kang J., Sarkar D., Khatami Y., Jena D., Banerjee K. Role of metal contacts in designing high-performance monolayer n-type WSe 2 field effect transistors. Nano Lett. 2013;13:1983–1990. doi: 10.1021/nl304777e. [DOI] [PubMed] [Google Scholar]

[bib59] 59.Chuang S., Battaglia C., Azcatl A., McDonnell S., Kang J.S., Yin X., Tosun M., Kapadia R., Fang H., Wallace R.M., Javey A. MoS2 P-type transistors and diodes enabled by high work function MoOx contacts. Nano Lett. 2014;14:1337–1342. doi: 10.1021/nl4043505. [DOI] [PubMed] [Google Scholar]

[bib60] 60.Liu Y., Guo J., Zhu E., Liao L., Lee S.-J., Ding M., Shakir I., Gambin V., Huang Y., Duan X. Approaching the Schottky–Mott limit in van der Waals metal–semiconductor junctions. Nature. 2018;557:696–700. doi: 10.1038/s41586-018-0129-8. [DOI] [PubMed] [Google Scholar]

[bib61] 61.Kwon G., Choi Y.-H., Lee H., Kim H.-S., Jeong J., Jeong K., Baik M., Kwon H., Ahn J., Lee E., Cho M.-H. Interaction- and defect-free van der Waals contacts between metals and two-dimensional semiconductors. Nat. Electron. 2022;5:241–247. doi: 10.1038/s41928-022-00746-6. [DOI] [Google Scholar]

[bib62] 62.Shen P.C., Su C., Lin Y., Chou A.S., Cheng C.C., Park J.H., Chiu M.H., Lu A.Y., Tang H.L., Tavakoli M.M., et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature. 2021;593:211–217. doi: 10.1038/s41586-021-03472-9. [DOI] [PubMed] [Google Scholar]

[bib63] 63.Li W., Fan D., Shao L., Huang F., Liang L., Li T., Xu Y., Tu X., Wang P., Yu Z. IEEE; 2021. High-performance CVD MoS 2 Transistors with Self-Aligned Top-Gate and Bi Contact; pp. 37.33.31–37.33.34. [Google Scholar]

[bib64] 64.Lin Y., Shen P.C., Su C., Chou A.S., Wu T., Cheng C.C., Park J.H., Chiu M.H., Lu A.Y., Tang H.L., et al. Contact engineering for high-performance N-type 2D semiconductor transistors. 2021;11:37.32.31–37.32.34. [Google Scholar]

[bib65] 65.Wang L., Meric I., Huang P.Y., Gao Q., Gao Y., Tran H., Taniguchi T., Watanabe K., Campos L.M., Muller D.A., et al. One-dimensional electrical contact to a two-dimensional material. Science. 2013;342:614–617. doi: 10.1126/science.1244358. [DOI] [PubMed] [Google Scholar]

[bib66] 66.Xiao J., Kang Z., Liu B., Zhang X., Du J., Chen K., Yu H., Liao Q., Zhang Z., Zhang Y. Record-high saturation current in end-bond contacted monolayer MoS2 transistors. Nano Res. 2022;15:475–481. doi: 10.1007/s12274-021-3504-y. [DOI] [Google Scholar]

[bib67] 67.Yang W., Sun Q.-Q., Geng Y., Chen L., Zhou P., Ding S.-J., Zhang D.W. The integration of sub-10 nm gate oxide on MoS2 with ultra low leakage and enhanced mobility. Sci. Rep. 2015;5:11921. doi: 10.1038/srep11921. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib68] 68.Zou X., Wang J., Chiu C.H., Wu Y., Xiao X., Jiang C., Wu W.W., Mai L., Chen T., Li J., et al. Interface engineering for high-performance top-gated MoS2 field-effect transistors. Adv. Mater. 2014;26:6255–6261. doi: 10.1002/adma.201402008. [DOI] [PubMed] [Google Scholar]

[bib69] 69.Hollander M.J., LaBella M., Hughes Z.R., Zhu M., Trumbull K.A., Cavalero R., Snyder D.W., Wang X., Hwang E., Datta S., Robinson J.A. Enhanced transport and transistor performance with oxide seeded high-κ gate dielectrics on wafer-scale epitaxial graphene. Nano Lett. 2011;11:3601–3607. doi: 10.1021/nl201358y. [DOI] [PubMed] [Google Scholar]

[bib70] 70.Li W., Zhou J., Cai S., Yu Z., Zhang J., Fang N., Li T., Wu Y., Chen T., Xie X., et al. Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices. Nat. Electron. 2019;2:563–571. [Google Scholar]

[bib71] 71.Li T., Tu T., Sun Y., Fu H., Yu J., Xing L., Wang Z., Wang H., Jia R., Wu J., et al. A native oxide high-κ gate dielectric for two-dimensional electronics. Nat. Electron. 2020;3:473–478. doi: 10.1038/s41928-020-0444-6. [DOI] [Google Scholar]

[bib72] 72.Zhang Y., Yu J., Zhu R., Wang M., Tan C., Tu T., Zhou X., Zhang C., Yu M., Gao X., et al. A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm. Nat. Electron. 2022;5:643–649. [Google Scholar]

[bib73] 73.Seabaugh A.C., Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE. 2010;98:2095–2110. doi: 10.1109/jproc.2010.2070470. [DOI] [Google Scholar]

[bib74] 74.Ionescu A.M., Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature. 2011;479:329–337. doi: 10.1038/nature10679. [DOI] [PubMed] [Google Scholar]

[bib75] 75.Khan A.I., Yeung C.W., Chenming H., Salahuddin S. IEEE; 2011. In 2011 International Electron Devices Meeting; pp. 11.13.11–11.13.14. [DOI] [Google Scholar]

[bib76] 76.Kim S., Myeong G., Shin W., Lim H., Kim B., Jin T., Chang S., Watanabe K., Taniguchi T., Cho S. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nat. Nanotechnol. 2020;15:203–206. doi: 10.1038/s41565-019-0623-7. [DOI] [PubMed] [Google Scholar]

[bib77] 77.Si M., Su C.J., Jiang C., Conrad N.J., Zhou H., Maize K.D., Qiu G., Wu C.T., Shakouri A., Alam M.A., Ye P.D. Steep-slope hysteresis-free negative-capacitance 2D transistors. Nat. Nanotechnol. 2018;13:24–28. doi: 10.1038/s41565-017-0010-1. [DOI] [PubMed] [Google Scholar]

[bib78] 78.Yu Z., Wang H., Li W., Xu S., Song X., Wang S., Wang P., Zhou P., Shi Y., Chai Y. IEEE; 2004. In 2017 IEEE International Electron Devices Meeting (IEDM) pp. 23.26.21–23.26.24. [Google Scholar]

[bib79] 79.Si M., Jiang C., Chung W., Du Y., Alam M.A., Ye P.D. Steep-slope WSe2 negative capacitance field-effect transistor. Nano Lett. 2018;18:3682–3687. doi: 10.1021/acs.nanolett.8b00816. [DOI] [PubMed] [Google Scholar]

[bib80] 80.Xiong X., Huang M., Hu B., Li X., Liu F., Li S., Tian M., Li T., Song J., Wu Y. A transverse tunnelling field-effect transistor made from a van der Waals heterostructure. Nat. Electron. 2020;3:106–112. [Google Scholar]

[bib81] 81.Qiu C., Liu F., Xu L., Deng B., Xiao M., Si J., Lin L., Zhang Z., Wang J., Guo H., et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science. 2018;361:387–392. doi: 10.1126/science.aap9195. [DOI] [PubMed] [Google Scholar]

[bib82] 82.Tang Z., Liu C., Huang X., Zeng S., Liu L., Li J., Jiang Y.G., Zhang D.W., Zhou P. A steep-slope MoS2/graphene Dirac-source field-effect transistor with a large drive current. Nano Lett. 2021;21:1758–1764. doi: 10.1021/acs.nanolett.0c04657. [DOI] [PubMed] [Google Scholar]

[bib83] 83.Yang J.J., Strukov D.B., Stewart D.R. Memristive devices for computing. Nat. Nanotechnol. 2013;8:13–24. doi: 10.1038/nnano.2012.240. [DOI] [PubMed] [Google Scholar]

[bib84] 84.Choi M.S., Lee G.-H., Yu Y.-J., Lee D.-Y., Lee S.H., Kim P., Hone J., Yoo W.J. Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices. Nat. Commun. 2013;4:1624. doi: 10.1038/ncomms2652. [DOI] [PubMed] [Google Scholar]

[bib85] 85.Ning Z., Olmedo M., Wang G., Liu J. Graphene based nickel nanocrystal flash memory. Appl. Phys. Lett. 2011;99:223312. [Google Scholar]

[bib86] 86.Hou X., Yan X., Liu C., Ding S., Zhang D.W., Zhou P. Operation mode switchable charge-trap memory based on few-layer MoS2. Semicond. Sci. Technol. 2018;33:034001. doi: 10.1088/1361-6641/aaa79e. [DOI] [Google Scholar]

[bib87] 87.Liu C., Yan X., Wang J., Ding S., Zhou P., Zhang D.W. Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2. Small. 2017;13:1604128. doi: 10.1002/smll.201604128. [DOI] [PubMed] [Google Scholar]

[bib88] 88.Chen M., Nam H., Wi S., Priessnitz G., Gunawan I.M., Liang X. Multibit data storage states formed in plasma-treated MoS transistors. ACS Nano. 2014;8:4023–4032. doi: 10.1021/nn501181t. [DOI] [PubMed] [Google Scholar]

[bib89] 89.Zhang E., Wang W., Zhang C., Jin Y., Zhu G., Sun Q., Zhang D.W., Zhou P., Xiu F. Tunable charge-trap memory based on few-layer MoS2. ACS Nano. 2015;9:612–619. doi: 10.1021/nn5059419. [DOI] [PubMed] [Google Scholar]

[bib90] 90.Mishra A., Kalita H., Waikar M., Gour A., Aslam M. 2012. Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory. [Google Scholar]

[bib91] 91.Bertolazzi S., Krasnozhon D., Kis A. Nonvolatile memory cells based on MoS2/graphene heterostructures. ACS Nano. 2013;7:3246–3252. doi: 10.1021/nn3059136. [DOI] [PubMed] [Google Scholar]

[bib92] 92.Li D., Chen M., Sun Z., Yu P., Liu Z., Ajayan P.M., Zhang Z. Two-dimensional non-volatile programmable p–n junctions. Nat. Nanotechnol. 2017;12:901–906. doi: 10.1038/nnano.2017.104. [DOI] [PubMed] [Google Scholar]

[bib93] 93.Zhang P., Li D., Chen M., Zong Q., Shen J., Wan D., Zhu J., Zhang Z. Floating-gate controlled programmable non-volatile black phosphorus PNP junction memory. Nanoscale. 2018;10:3148–3152. doi: 10.1039/c7nr08515j. [DOI] [PubMed] [Google Scholar]

[bib94] 94.Vu Q.A., Shin Y.S., Kim Y.R., Nguyen V.L., Kang W.T., Kim H., Luong D.H., Lee I.M., Lee K., Ko D.S., et al. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio. Nat. Commun. 2016;7:12725. doi: 10.1038/ncomms12725. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib95] 95.Vu Q.A., Kim H., Nguyen V.L., Won U.Y., Adhikari S., Kim K., Lee Y.H., Yu W.J. A high-on/off-ratio floating-gate memristor array on a flexible substrate via CVD-grown large-area 2D layer stacking. Adv. Mater. 2017;29:1703363–1703367. doi: 10.1002/adma.201703363. [DOI] [PubMed] [Google Scholar]

[bib96] 96.Liu C., Yan X., Wang J., Ding S., Zhou P., Zhang D.W. Eliminating overerase behavior by designing energy band in high-speed charge-trap memory based on WSe2. Small. 2017;13:1604128. doi: 10.1002/smll.201604128. [DOI] [PubMed] [Google Scholar]

[bib97] 97.Liu C., Yan X., Song X., Ding S., Zhang D.W., Zhou P. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications. Nat. Nanotechnol. 2018;13:404–410. doi: 10.1038/s41565-018-0102-6. [DOI] [PubMed] [Google Scholar]

[bib98] 98.Ding Y., Liu L., Li J., Cao R., Jiang Y.G., Liu C., Liu Q., Zhou P. A semi-floating memory with 535% enhancement of refresh time by local field modulation. Adv. Funct. Mater. 2020;30:1908089. doi: 10.1002/adfm.201908089. [DOI] [Google Scholar]

[bib99] 99.Wu L., Wang A., Shi J., Yan J., Zhou Z., Bian C., Ma J., Ma R., Liu H., Chen J., et al. Atomically sharp interface enabled ultrahigh-speed non-volatile memory devices. Nat. Nanotechnol. 2021;16:882–887. doi: 10.1038/s41565-021-00904-5. [DOI] [PubMed] [Google Scholar]

[bib100] 100.Liu L., Liu C., Jiang L., Li J., Ding Y., Wang S., Jiang Y.G., Sun Y.B., Wang J., Chen S., et al. Ultrafast non-volatile flash memory based on van der Waals heterostructures. Nat. Nanotechnol. 2021;16:874–881. doi: 10.1038/s41565-021-00921-4. [DOI] [PubMed] [Google Scholar]

[bib101] 101.Dorow C.J., O’Brien K.P., Naylor C.H., Lee S., Penumatcha A., Hsiao A., Tronic T., Christenson M., Maxey K., Zhu H., et al. Vol. 13. 2021. pp. 1–2. (Advancing monolayer 2D NMOS and PMOS transistor integration from growth to van der Waals interface engineering for ultimate CMOS scaling). [Google Scholar]

[bib102] 102.Li X., Cai W., An J., Kim S., Nah J., Yang D., Piner R., Velamakanni A., Jung I., Tutuc E., et al. Large-area synthesis of high-quality and uniform graphene films on copper foils. Science. 2009;324:1312–1314. doi: 10.1126/science.1171245. [DOI] [PubMed] [Google Scholar]

[bib103] 103.Chou A.S., Wu T., Cheng C.C., Zhan S.S., Ni I.C., Wang S.Y., Chang Y.C., Liew S.L., Chen E., Chang W.H., et al. Vol. 11. 2021. pp. 7.2.1–7.2.4. (Antimony semimetal contact with enhanced thermal stability for high performance 2D electronics). [Google Scholar]

[bib104] 104.Das S., Chen H.-Y., Penumatcha A.V., Appenzeller J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 2013;13:100–105. doi: 10.1021/nl303583v. [DOI] [PubMed] [Google Scholar]

[bib105] 105.Xie L., Jiao L., Dai H. Selective etching of graphene edges by hydrogen plasma. J. Am. Chem. Soc. 2010;132:14751–14753. doi: 10.1021/ja107071g. [DOI] [PubMed] [Google Scholar]

[bib106] 106.Ryu G.H., Zhu T., Chen J., Sinha S., Shautsova V., Grossman J.C., Warner J.H. Striated 2D lattice with sub-nm 1D etch channels by controlled thermally induced phase transformations of PdSe2. Adv. Mater. 2019;31:1904251. doi: 10.1002/adma.201904251. [DOI] [PubMed] [Google Scholar]

[bib107] 107.Zhou J., Zhang C., Shi L., Chen X., Kim T.S., Gyeon M., Chen J., Wang J., Yu L., Wang X., et al. Non-invasive digital etching of van der Waals semiconductors. Nat. Commun. 2022;13:1844–1848. doi: 10.1038/s41467-022-29447-6. [DOI] [PMC free article] [PubMed] [Google Scholar]

[bib108] 108.Liao L., Lin Y.-C., Bao M., Cheng R., Bai J., Liu Y., Qu Y., Wang K.L., Huang Y., Duan X. High-speed graphene transistors with a self-aligned nanowire gate. Nature. 2010;467:305–308. doi: 10.1038/nature09405. [DOI] [PMC free article] [PubMed] [Google Scholar]

PERMALINK

2D materials readiness for the transistor performance breakthrough

Qing Zhang

Chunsen Liu

Peng Zhou

Summary

Introduction

Discussion and results

The ultrasmall gate-length transistor demonstration

Figure 1.

Alternative scaling route: Single logic transistor

Figure 2.

The contacts optimization of 2D transistors

Figure 3.

The integration of ultrathin HIGH-κ dielectric on 2D materials

Figure 4.

The steep SS 2D transistors

Figure 5.

The ultrafast floating-gate transistor

Figure 6.

Conclusion and outlook

Acknowledgments

Author contributions

Declaration of interests

Inclusion and diversity

Contributor Information

References

ACTIONS

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Cite

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PERMALINK

2D materials readiness for the transistor performance breakthrough

Qing Zhang

Chunsen Liu

Peng Zhou

Summary

Introduction

Discussion and results

The ultrasmall gate-length transistor demonstration

Figure 1.

Alternative scaling route: Single logic transistor

Figure 2.

The contacts optimization of 2D transistors

Figure 3.

The integration of ultrathin HIGH-κ dielectric on 2D materials

Figure 4.

The steep SS 2D transistors

Figure 5.

The ultrafast floating-gate transistor

Figure 6.

Conclusion and outlook

Acknowledgments

Author contributions

Declaration of interests

Inclusion and diversity

Contributor Information

References

ACTIONS

PERMALINK

RESOURCES

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