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. 2023 Jun 8;5(6):3309–3315. doi: 10.1021/acsaelm.3c00350

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN

Jinggui Zhou †, Huy-Binh Do ‡, Maria Merlyne De Souza †,*
PMCID: PMC10308811  PMID: 37396055

Abstract

graphic file with name el3c00350_0006.jpg

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | – 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

Keywords: 2DHG, E-mode, GaN, MOSFET, p-channel, n-channel, AlGaN, graded channel

Introduction

Gallium nitride (GaN) power devices utilizing a two-dimensional electron gas (2DEG) are promising in applications requiring high voltage, high speed, and low power consumption due to the superior wide-bandgap material properties in comparison with silicon.1−3 The monolithic integration of a power device with its gate driver is required to suppress oscillations during high-frequency operation that can irrevocably damage the device.4 GaN-based p-channel devices offer the possibility of on-chip complementary logic; however, owing to the low mobility, poor current density, and high resistivity of contacts, such devices are not yet in manufacture.

Several p-channel devices with polarization-induced two-dimensional hole gas (2DHG) at the heterointerface have been reported.5−10 Similar to a 2DEG, the 2DHG has characteristics of high density and temperature independence.11 However, to achieve a GaN-based complementary metal-oxide-semiconductor (CMOS) technology, p-channel devices with high on-current, enhancement-mode (E-mode), and high on/off ratio are desired to be integrated with a related n-channel power device on the same platform.7,12−15 Recently, due to the commercialization of E-mode p-GaN gate high electron mobility power transistors (HEMTs),1 p-channel MOSFETs (pFETs) with the same p-GaN/AlGaN/GaN-based epitaxial structure have attracted great interest.16−19 Among them, E-mode pFETs with (ION/IOFF) of 3 × 108 and a high threshold voltage (Vth) of | – 2.2 V| were demonstrated.19 However, the improved on-current (ION) of 18.5 mA/mm by 1.5 nm AlN spacer19 is still much lower than that of a generic E-mode n-channel device.20 Moreover, in a GaN/AlGaN/GaN-based architecture, an ION of 125 mA/mm was attained at VDS = – 20 V for the p-FETs with Schottky gate structure,21 but the limitation of leakage in a Schottky gate causes ION/IOFF < 105. On the other hand, an ultrawide bandgap semiconductor AlN/GaN/AlN-based platform shows potential to increase the current density by maximizing the polarization discontinuity22−24 and indicates excellent output power performance in mm-wave integrated circuits,25,26 which makes it promising in RF and high-power application. A remarkable ION of 428 mA/mm was obtained in a pFET on this platform,24 with an ION/IOFF of 102 and Vth of 4 V. Recently, ION > 100 mA/mm and ION/IOFF > 107 were achieved by a self-aligned gate and FinFET architecture based on the p-GaN/u-GaN/AlGaN/GaN epitaxial structure.27 However, normally off operation was achieved by a 40 nm fin width and 50 nm gate recess which can easily convert the device into D-mode if not accurately controlled, as pointed out by the authors. Moreover, a p-GaN/u-GaN/1.5 nm AlN/AlGaN-based p-channel self-aligned FinFET with a fin width of 20 nm was shown to realize an ION of 300 mA/mm but an ION/IOFF ratio of only 200.28 Furthermore, besides gate length, reducing gate width can improve the mobility and current density in GaN HEMTs, and the effective modulation of ION, IOFF, and electric field makes the gate width a key parameter for further optimization of GaN HEMTs.29

Considering the commercial maturity of the p-GaN/AlGaN /GaN platform and to avoid impurity scattering at the p-GaN/AlGaN interface, a p-GaN/u-GaN/AlGaN/GaN epitaxial structure, with the potential for monolithic integration without any regrowth, is selected in this work. In addition, the graded AlGaN layer can benefit the linearity and breakdown voltage of GaN HEMTs in RF applications.30 We examine the impact of the densities of 2DHG and 2DEG on the performance of a p-channel FET via simulation and explore graded AlGaN barriers to alleviate the tradeoff between the densities of the 2DHG and 2DEG.

Methodology

Figure 1a shows the schematic of the platform consisting from top to bottom of 20 nm of p++GaN doped with Mg concentration of 6 × 1019 cm–3, 50 nm of p+GaN (Mg: 1 × 1019 cm–3), 20 nm of undoped GaN (u-GaN) as a channel layer (tch), and 20 nm of Al0.2Ga0.8N barrier layer (tb) below which lies a 150 nm-thick u-GaN and buffer layer reported in ref (13). Our simulations are first benchmarked based on the reported epitaxial stack in Silvaco TCAD using a gate length (LG) of 2 and 4 μm for p-channel and n-channel devices, respectively, reported in ref (13). The source to drain distance (LSD) is 6 and 12 μm for the p- and n-FET, respectively. In the p-FET, the gate oxide is 20 nm Al2O3, with the recessed gate etched out of the p++GaN and p+GaN to support E-mode operation. Based on Hall measurements, a mobility value of 10 cm2/Vs of holes in a 2DHG is used.13Figure S1 reveals that the mobility of holes in the 3DHG is ∼10.4 cm2/Vs and its peak value changes relatively with the density of 3DHG in the graded AlGaN in our simulation model (Supporting Information A). In addition, a negative fixed interface charge and trap density at the oxide/GaN interface of 6.4 × 1012 and 3 × 1012 cm–2, respectively, are introduced in our model to match the reported experimental ID – VGS curves in Figure 1b.13 Two kinds of graded AlGaN barriers are introduced in this work. Along the [0001] growth direction, the negatively graded AlGaN has an Al mole fraction (Xb) that is linearly reduced from the bottom (Xb. bottom, close to the buffer layer) to the top (Xb. top, close to the u-GaN channel), viz., ΔXb. n = Xb. bottom – Xb. top. On the other hand, a positively graded AlGaN has an opposite structure, i.e., ΔXb. p = Xb. top – Xb. bottom. In addition, several new kinds of composite barriers with varied thickness of negatively graded barriers (tb. n) and positively graded barrier (tb. p) are listed in Table 1. Barrier A is a single negatively graded AlGaN layer with fixed Xb. bottom and varied Xb. top displayed in Figure 1c. Figure 1d exhibits a dual back-to-back graded AlGaN Barrier B, and the upper layer is negatively graded AlGaN with 25% Xb. bottom and changed Xb. top, whereas the layer beneath is positively graded AlGaN with 25% Xb. top and varied Xb. bottom. ΔXb. p is kept the same as ΔXb. n. In this work, our assumption of a 4.95% Al/nm gradient31 and 5 nm graded AlGaN with 23% ΔXb. p32 make the 5 nm graded AlGaN with 25% gradient to be practically possible. Considering that the p-GaN gate in n-FETs on this platform requires layers to be etched up to the positively graded AlGaN, a precise etch stop at the negative/positively graded AlGaN interface is essential.

Figure 1.

Figure 1

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(a) Schematic of the benchmarked p-FET and n-FET from.13 (b) Verification of the simulation models with experimental ID – VG characteristics13 of p-FET and n-FET in Silvaco TCAD. Reprinted with permission from ref (13). Copyright [2020][IEEE Electron Device Lett.]. The platform structure consists of: (c) Barrier A: A single negatively graded AlGaN. (d). Barrier B: Composite AlGaN, the upper layer is negatively graded AlGaN with Xb. bottom = 25% on top of a positively graded AlGaN with fixed Xb. top = 25%.

Table 1. Details of Optimized Barrier Layers.

ID barrier parameters
barrier A negatively graded AlGaN
barrier A1 tb. n = 20 nm, Xb. bottom = 20%
arrier A2 tb. n = 20 nm, Xb. bottom = 25%
ID upper layer parameters lower layer parameters
barrier B negatively graded AlGaN, Xb. bottom = 25% positively graded AlGaN, Xb. top = 25%
barrier B1 tb. n = 5 nm tb. p = 15 nm
barrier B2 tb. n = 10 nm tb. p = 10 nm
barrier B3 tb. n =1 5 nm tb. p = 5 nm
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Results and Evaluation

To examine the influence of the underlying 2DEG density on the performance of p-FETs, the Al0.2Ga0.8N barrier layer of the epitaxial structure in Figure 1a is replaced by Barrier A1, whereas the effects of a single positively graded AlGaN (counterpart of Barrier A) on both n- and p-channel FETs are shown in Figure S2 (Supporting Information B). Figure 2a reveals that the hole density (nH) increases as the underlying electron density (nE) is reduced by an increase of ΔXb. n. Although a 1.5 times improvement is achieved for nH with 10% ΔXb. n, nE reduces dramatically by 12 orders and below a value of 10/cm2, which will severely degrade n-channel devices. According to Figure 2b, for Barrier A1, when ΔXb. n is increased to 8%, the on-current (|ION|) of the PMOS is doubled compared with the standard device with Al0.2Ga0.8N barrier at VDS = – 0.5 V, whereas the on/off ratio (ION/IOFF) reduces from 105 to 100. In contrast, a threefold drop of ION occurs in the n-channel device with Barrier A1 as ΔXb. n is raised from 0 to 8% as shown in the inset of Figure 2b, which means the negatively graded barrier unilaterally benefits ION for p-FETs. Moreover, unlike in p-FETs, ION/IOFF in n-FETs is immune to the changes of ΔXb. n and nE. The reason is because although graded AlGaN barriers redistribute channel carriers, the off-state current (IOFF) of n-channel devices, in practice, is mainly affected by traps in the buffer layer- or surface-related conduction.33

Figure 2.

Figure 2

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(a) nH in p-channel and nE in n-channel with respect to a change in ΔXb. n based on the platform with Barrier A1. (b) ION and ION/IOFF as a function of ΔXb. n at VDS= −0.5 V for PMOS with Barrier A1. The inset indicates ION and ION/IOFF as a function of ΔXb. n at VDS = 0.5 V for NMOS with Barrier A1.

This one-way gain makes the single-graded barrier layer disadvantageous to p- or n-channel devices and complementary integration, and requires an additional positively graded AlGaN below the negatively graded AlGaN layer (Figure 1d) as investigated in Figure 3a. It is obvious from Figure 3a that with Barrier B, both nE and nH show degradation with increased ΔXb. n(b. p) when the thickness of the positively graded AlGaN tb. p increases, which means polarization-induced holes and electrons in a back-to-back graded AlGaN with optimized tb. n, tb. p, and ΔXb. n(b. p) are mutually restricted instead of unilaterally suppressed. In this structure, the optimized tradeoff points between nH and nE are obtained in Barrier B3 with ΔXb. n(b. p) = 7% resulting in a concentration of ∼7.8 × 1012cm–2for both holes and electrons.

Figure 3.

Figure 3

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(a) Comparison of nH and nE as a function of ΔXb. n in the composite AlGaN barriers of tb = 20 nm that consist of Barriers B1, B2, and B3. (b) Comparison of band diagram and distribution of hole concentration between the devices with fixed Al0.25Ga0.75N barrier layer, Barrier A2 with 15 and 25% ΔXb. n and Barriers B1, B2, and B3 with 25% ΔXb. n at Vg = Vd = 0 V.

Figure 3b demonstrates that the hole quantum well is weakened by the negatively graded barrier layer at the u-GaN channel/AlGaN barrier interface. When comparing Al0.25N0.75 with Barrier A2, the larger ΔXb. n introduces a curvature of the barrier layer, resulting in the quantum well at the u-GaN/AlGaN junction becoming flatter and wider. It is observed that in Barrier A2, this “flat” quantum well not only accumulates a 2DHG at the u-GaN/AlGaN interface but also induces a three-dimensional hole gas (3DHG) in the barrier layer. It is well known that a graded barrier layer results in polarization doping without impurity dopants, which can improve the conductivity of the graded layer.34 In addition, as ΔXb. n reaches the maximum value of 25%, the 2DHG at the u-GaN/AlGaN interface in Barrier A2 disappears and only a broad and flat 3DHG distribution in the barrier layer is observed. This 3DHG also broadens the channel width to achieve a higher current density in p-FETs. However, the conduction band at the AlGaN/GaN buffer interface is raised away from the Fermi level in Barrier A2 due to the large ΔXb. n, which contributes to the potential in the barrier layer being shifted toward negative values and the hole confinement subsequently reduced in Barrier A2. As a result, the ability of the polarization field for blocking punch-through leakage paths into the buffer layer is weakened.

On the other hand, when the positively graded AlGaN is introduced, it is seen from Figure 3b that the conduction band reverts to the Fermi level at VGS = 0 V and lies below the Fermi level at the AlGaN/GaN interface with an extension into the AlGaN barrier layer. The band offset in Barrier B with a thicker tb. p is larger and sharper. Consequently, the width and peak of the 3DHG across the negatively graded barrier are limited by tb. p as shown in Figure 3b. Thus, despite the maximum ΔXb. n, nH still reduces with larger tb. p as Figure 3a indicates. Furthermore, Figure 3b illustrates that based on Barriers B2&B3 with 25% ΔXb. n(b. p), quantum wells at the GaN channel/AlGaN and AlGaN/GaN buffer interfaces both turn “flat” and are pinned to the Fermi level with a large band offset at the AlGaN/GaN interface. Consequently, the distributions of the potential and polarization-induced charges are rebuilt in the barrier layer with excellent hole confinement in the channel, which is surmised to suppress the leakage in p-channel devices.

Abstract figure displays the new back-to-back graded AlGaN barrier-based platform for complementary integration. To achieve an E-mode and high ION/IOFF for PMOS, a gate recess depth in the u-GaN channel layer (trecess) of 18 nm is used. Moreover, in n-channel devices, to prevent degradation of on-current caused by the reduced nE as shown in Figure 3a, the top negative AlGaN is etched away beneath the p-GaN gate. Barrier B3 with a tradeoff of 7% ΔXb. n and a maximum of 25% ΔXb. n are applied to NMOS with LG = 4 μm and scaled PMOS with LG = 1 μm as shown in Figure 4a,b. Figure 4a reveals that the on-state current density of p-channel devices with Barrier B3 is increased compared to the counterpart with a fixed Al mole fraction due to the polarization doping and enlarged nH by a negatively graded AlGaN. In addition, unlike the deterioration of ION/IOFF in a single negatively graded AlGaN, ION/IOFF > 1012 with Barrier B3 and the large ΔXb. n prove that the positively graded AlGaN improves hole confinement and band offset in the composite AlGaN barrier to suppress the leakage current into the GaN buffer layer in the PMOS in Figure 3b.

Figure 4.

Figure 4

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Black line: fixed Al0.25Ga0.75N barrier layer; Red line: Barrier B3 with 7% ΔXb. n(b. p); Blue line: Barrier B3 with 25% ΔXb. n(b. p). (a) Comparison of the transfer characteristics in linear and log scale between PMOS with different barriers at LG = 1 μm, LSD = 3 μm, trecess = 18 nm, and VD = – 5 V. (b) ID – VGS characteristics in log and linear scale of n-channel devices based on the same platform as Abstract figure at LG = 4 μm, LSD = 12 μm, and VD = 5 V. (c) Comparison of the ID – VGS curves in linear and log scale between the scaled PMOS with Al0.25Ga0.75N and Barrier B3 at LG = 200 nm, LSD = 600 nm, trecess = 18 nm, and VD = – 5 V. The inset reveals ID and ION/IOFF at VD = VGS = – 5 V with a change in gate length with fixed LSG = LGD = 1 μm for PMOS with Barrier B3. (d) Comparison of current density around the u-GaN channel/AlGaN interface under the gate and access region between PMOS with various barriers at LG = 200 nm, LSD = 600 nm, and VD = VGS = – 5 V.

At VD = VGS = 5 V, ION of n-channel devices with Barriers B3 is improved by 19.7% compared with a device with fixed Al mole fraction as shown in Figure 4b. Similar to the role of a negatively graded AlGaN in PMOS, the positively graded AlGaN enhances the channel depth with 3DEG polarization doping and redistributes the potential and electrons in n-channel devices, which means the mutual limitation between the hole and electron channels in the GaN/AlGaN/GaN-based epitaxial platform and the decrease of ION induced by the p-GaN gate in n-channel devices is overcome by the back-to-back graded AlGaN. In addition, n-channel devices with Barrier B3 all reveal a drift of Vth toward the positive direction with no change in the off-state current level. The reason is that the negatively graded AlGaN in the p-GaN gate region depletes the electrons below and IOFF in n-FETs is dominated by surface-related conduction and buffer layer characteristics.33 To realize a better gate electrostatic control for n-FETs, the thinner u-GaN channel thickness and fin-gate structure are feasible. Moreover, Figure S3b illustrates the effects of under-etch and over-etch of the p-GaN gate region on the performance of n-FETs (Supporting Information C). The maximum degradation of ION observed is ∼30%. Furthermore, we have shown that the figure of merit (FOM = VBV2/Ron, sp) can be improved by 3 times in a GaN power HEMT with the back-to-back graded AlGaN compared to the one with a conventional Al0.25Ga0.75N.35

The impact of gate length scaling is investigated at VD = VGS = – 5 V in Figure 4c, via a Barrier B3-based PMOS, with LG = 200 nm and LSD = 600 nm, which is shown to increase |ION| from 45mA/mm, for a fixed Al0.25Ga0.75N barrier, to 65mA/mm with large ION/IOFF of ∼1012 and threshold voltage | – Vth| of | – 1.3 V|. A further improvement of |ION| of 23% with | – Vth| of | – 0.9 V| with Barrier B3 is possible with 25%ΔXb. n; however, ION/IOFF decreases significantly by 5 orders, which indicates that in a shorter gate, it is difficult to deplete holes with a wider channel depth. The inset of Figure 4c illustrates that |ION| of the PMOS with Barrier B3 of 7% ΔXb. n is increased by 39% when LG is reduced from 1 μm to 90 nm with source-to-gate (LSG) and gate-to-drain (LGD) length maintained at 1 μm. Meanwhile, ION/IOFF of the PMOS with Barrier B3 of 7%ΔXb. n stays above 1012 as LG ≥ 200 nm. The inset of Figure 4c also indicates that although the larger hole spread of Barrier B3 of 25%ΔXb. n enhances |ION| during scaling of LG, ION/IOFF is worsened significantly owing to insufficient depletion region across the 3DHG slab.

Figure 4d demonstrates a comparison of the current density distribution from a u-GaN channel to the AlGaN barrier under the gate region (IDen. Gate) and the access region between the gate and drain (IDen. Access) in a PMOS with Al0.25Ga0.75N and Barrier B3 at 200 nm LG. In Figure 4d, at −5 V of VD and VGS, IDen. Gate, and IDen. Access both achieve a spread distribution across the AlGaN barrier with Barrier B3 with 25% ΔXb. n-based PMOS, which proves that the extended “flat” quantum well at the u-GaN/AlGaN interface. This occurs because a large gradient leads to holes drifting into the negative barrier layer instead of the limited 2-dimensional transport direction in the abrupt quantum well and also leakage currents are more likely to flow through these areas. Furthermore, 25% ΔXb. n induces the widest 3DHG slab across the barrier, which results in an improved barrier conductivity and broadened current flow path that is difficult to be depleted and controlled by a short gate. Therefore, the leakage current is more controllable in Barrier B3 with 7% ΔXb. n during gate scaling. Utilizing a fin gate configuration has the potential to suppress the leakage current and take full advantage of the back-to-back graded AlGaN barrier with large gradient.

Conclusions

This work provides a new back-to-back graded barrier platform for GaN-based CMOS. It is seen that the underlying 2DEG of PMOS is lowered by increasing ΔXb. n in the negatively graded AlGaN buffer layer, which results in a significantly higher on-current density. A recess gate E-mode p-channel MOSFET with LG = 200 nm and trecess = 18 nm demonstrates |ION| = 65mA/mm, ION/IOFF ≈ 1012 and | – Vth| = | – 1.3 V| is realized by the back-to-back graded barrier with an optimum 7% ΔXb. n(b. p). Furthermore, for the back-to-back graded AlGaN barrier layer, not only does the negatively graded AlGaN on the top result in high current density and conductivity in p-channel devices but also the positively graded AlGaN below contributes to a rise of the on-state current by 19.7% in n-channel devices.

Acknowledgments

This work was motivated by the EPSRC through Challenge Network Grant CN/FEAS/PCON.

Supporting Information Available

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsaelm.3c00350.

  • Mobility model for 2DHG and 3DHG; effects of single positively graded barrier on n-FETs and p-FETs; influences of the under-etch and over-etch for p-GaN gate region on n-FETs (PDF)

The authors declare no competing financial interest.

Supplementary Material

el3c00350_si_001.pdf (477.3KB, pdf)

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