0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-Input/Output Differential Difference Transconductance Amplifiers

Abstract

This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.

1. Introduction

Active analog blocks, such as the operational amplifier (OA) or the transconductance amplifier (TA), are essential components for electronic devices, communication systems, and sensor interfaces. These blocks typically use the standard two inputs (i.e., a single differential stage). However, it has been confirmed that the use of a block with multiple inputs can reduce the number of components, silicon area, and power dissipation of some applications by a factor of approximately k, where k is the number of TA inputs [1]. Several applications based on this concept have been presented in [1,2,3,4]. Some other examples of multiple-input blocks are the differential difference amplifier (DDA) [5,6,7,8,9], differential difference current conveyor (DDCC) [10,11], differential difference operational floating amplifier (DDOFA) [12], differential difference transconductance amplifier (DDTA) [13,14], and many others. All these blocks allow for more arithmetic operations due to their multiple-input capabilities and are therefore widely used in instrumentation amplifiers, signal conditioning, differential amplification, filters, and many other applications. Although these blocks can reduce an application’s complexity and the number of blocks utilized, their internal structure is more complex than that of a standard two-input block. This is primarily due to the increased number of differential stages that are required to increase the number of inputs. The multiple-input MOS transistor (MI-MOST) provides a solution to avoid this problem and maintain a single differential stage [15,16,17]. It can be used in any standard CMOS technology without constraints. The first experimental results of MI-MOST are presented in [15,16,17] and various applications based on MI-MOST are presented in [18,19,20,21,22,23,24].

Filters play an important role in electronic, telecommunication and control systems. They can be used to reduce harmonics and filter noise in an electronic system, to separate or select desired signals, to remove unwanted signals in telecommunication systems, or to reduce the noise component of measurement signals in a control system. There are five common filtering functions that can be classified, namely the low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF). These filtering functions can be designed using passive and active components, called passive filters or active filters, respectively. Second-order filters (or biquad filters) can be used to realize high-order filters applied to a high-fidelity three-ways crossover loudspeaker network and to a phase-locked loop.

Using active device-based filters, second-order LPF, HPF, BPF, BSF and APF (five filter functions) can be provided in a single topology, creating the so-called universal filter. Circuits that can provide voltage-mode (VM) (input and output as voltage), current-mode (CM) (input and output as current), transadmittance-mode (TAM) (input as voltage and output as current) and transimpedance-mode (TIM) (input as current and output as voltage) transfer functions in the same circuit are classified as mixed-mode universal filters. In a perfect mixed-mode universal filter, each mode of the transfer function should provide five filter functions, therefore obtaining twenty filter functions in a single topology. In addition, perfect universal filters should have high input impedance and low output impedance if the input and output are in voltage forms and low input and high output impedance if the input and output are in current forms.

There are many mixed-mode universal filters available in the literature [25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61]. The circuits in [25,26,27,28,29,30,31,32,33,34,35,36,37,38] realize a mixed-mode universal filter using variant active devices such as current conveyors [25,26,27,28,29,30,31,32,33,34], the CFOA (current feedback operational amplifier) [35,36,37], the FTFN (four terminal floating nullor) [38]; however, these filters lack electronic tuning capabilities. The circuits in [39,40,41] use current-controlled current conveyor-based filters to offer electronic tuning capability, but the circuits in [39,40,42] do not provide twenty transfer functions and the circuits in [41,42] require input matching conditions.

To obtain electronic tuning capability, the circuits in [43,44,45,46] use the CCTA (current conveyor transconductance amplifier), the circuit in [47] uses the VDTA (voltage differencing transconductance amplifier), the circuits in [48,49] use the VD-DVCC (voltage differencing differential voltage current conveyor), and the circuits in [50,51] use the VDBA (voltage differencing buffered amplifier). However, the circuits in [43,46,47] do not offer twenty transfer functions, the circuits in [48,49] require active/passive component matching conditions, and the circuits in [50,51] apply input voltage signals via a passive capacitor and/or resistor.

The OTA (operational transconductance amplifier) has been used to realize mixed-mode universal filters [52,53,54,55,56,57,58,59,60]. However, the circuits in [52,54,59] require passive or active components, the circuits in [53,56,57] do not provide twenty transfer functions, and the circuits in [52,53,58,60] require inverted input signals. It should be noted that the structure of active devices used in [25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60] is not designed for low-voltage low-power filters. Filters for such applications are in high demand, especially for biosignal and sensor signal processing. Many filters based on multiple-input DDTA have been presented [61,62,63,64,65,66,67,68].

This paper presents a versatile mixed-mode filter using MIMO-DDTAs. The circuit has six input voltages, three input currents, three output voltages, and two output currents; as such, it offers 61 transfer functions of LPF, BPF, HPF, BSF, and APF in the same topology. The six input voltage terminals possess a high-impedance level, and the three output voltage nodes possess a low-impedance level, which is ideal for voltage-mode circuits. The two output current terminals also possess a high-impedance level which can be connected directly to loads without buffer circuit requirements. The natural frequency of the filters can also be controlled electronically. The proposed versatile mixed-mode filter uses a supply voltage of 0.5 V and 281 nW of power consumption.

The paper is organized as follows: Section 2 describes the multiple-input/output DDTA. Section 3 describes the application of the versatile mixed-mode filter and non-ideality analysis. Section 4 presents the simulation results. Finally, the conclusion is given in Section 5.

2. Proposed DDTA Circuit with Multiple-Input and Multiple-Output

The electrical symbol of the proposed multiple-input/output differential-difference transconductance amplifier is shown in Figure 1. Its performance, in an ideal case, is described by Equation (1). The circuit possesses one low-impedance output w, which provides a difference of the sums of the voltages V_y+ and V_y−, applied to its non-inverting and inverting terminals, respectively. It further has a high-impedance output o, which provides a current, proportional to the voltage V_w appearing at the w terminal.

$$\left.\begin{array}{c}{V}_w=V_{y+1}+V_{y+2}-V_{y-1}-V_{y-2}\\ I_{o\pm }=\pm g_m{V}_w\end{array}\right\}$$ (1)

Figure 1.

Electrical symbol of the MIMO-DDTA.

The CMOS structure of the proposed circuit is shown in Figure 2. The circuit consists of two blocks, a multiple-input differential-difference amplifier (MI-DDA) and a multiple-output transconductance amplifier (MO-TA).

Figure 2.

CMOS structure of the MIMO-DDTA.

The MI-DDA can be seen as a two-stage internal OTA, operating in a unity-gain feedback configuration. The first gain stage is formed by the transistors M₁–M₁₂, M₁₄, M₁₅, while the second stage is formed by the transistors M₁₃ and M₁₆. The capacitance C_C is used for frequency compensation. The first stage can be seen as a current-mirror OTA, with a differential amplifier M₁–M₁₀ and a set of current mirrors M₅–M₁₂, M₆–M₁₁, M₁₄–M₁₅, acting as a differential to a single output converter.

The input stage is based on a non-tailed bulk-driven differential pair M₁-M₄, which behaves as a differential amplifier with high CMRR and PSRR performances, while also being able to operate at extremely low supply voltages [69], even lower than the threshold voltages of the used MOS transistors. In order to increase the voltage gain, a partial positive feedback (PPF) is applied. The PPF is created by two cross-coupled transistor pairs: M₇–M₈ and M₉–M₁₀. The cross-coupled pairs generate negative conductances that partially compensate for the conductances of the diode-connected transistors M_2A,B for the “upper” pair, and M₅, M₆ for the “lower” pair. Therefore, the resulting conductances increase at the drains of these transistors, and, consequently, the first stage transconductance and voltage gain also increase. In particular, the upper pair increases the voltage gain from the bulk terminals to the gates of M_1A,B [70], while the lower pair increases the current gains of the current mirrors M₅–M₁₂ and M₆–M₁₁ [71]. The combination of two PPF circuits decreases the overall sensitivity of the transconductance gain of the first stage to transistor mismatch [63]. This achieves a larger voltage gain while maintaining relatively low sensitivity of the input stage and avoiding problems with frequency compensation of the DDA.

In order to realize a differential to difference function without duplicating the input stage, the multiple inputs were realized using the so-called multiple-input BD MOS transistors [15]. The symbol and the implementation of the devices are shown in Figure 3a,b, respectively. A passive capacitive voltage divider is applied to the bulk terminal of the MOS transistor, thus creating a multiple-input device. The large resistors R_MOSi, used to bias the bulk terminal for DC, are realized using two minimum-size MOS transistors operating in a cut-off region, as shown in Figure 3c.

Figure 3.

MI-BD MOST: (a) symbol, (b) possible implementation, (c) implementation of R_MOS.

Assuming 1/ωC_Bi << R_MOSi, the voltage V_b at the bulk terminal of the MI-BD-MOS transistor can be expressed as:

$$V_b={\sum }_{i=1}^n{\beta }_i{V}_i$$ (2)

where n is the number of inputs and β_i is the voltage gain of the input capacitive divider:

$${\beta }_i=\frac{C_{Bi}}{{\sum }_{i=1}^n{C}_{Bi}}$$ (3)

Note that with equal C_Bi, β_i = 1/n.

The open-loop voltage gain of the DDA can be expressed as:

$$A_{vo}=\beta \frac{2g_{mb1}\left(r_{ds15}\left|\right|r_{ds12}\right)g_{m16}\left(r_{ds16}\left|\right|r_{ds13}\right)}{\left(1-m_1\right)\left(1-m_2\right)}$$ (4)

where the coefficients m₁ and m₂ are the ratios of the absolute values of the negative and positive conductances in a lower and upper PPF circuit, respectively [62]:

$$m_1=\frac{g_{m\mathrm{9,10}}}{g_{m\mathrm{5,6}}+g_{ds2}+g_{ds\mathrm{3,4}}+g_{ds\mathrm{7,8}}}\cong \frac{g_{m\mathrm{9,10}}}{g_{m\mathrm{5,6}}}$$ (5)

$$m_2=\frac{g_{m\mathrm{7,8}}}{g_{m2}+g_{ds1}+g_{ds\mathrm{5,6}}+g_{ds\mathrm{9,10}}}\cong \frac{g_{m\mathrm{7,8}}}{g_{m2}}$$ (6)

Note that the above coefficients should always be lower than unity to maintain circuit stability. In the proposed design, m₁ = m₂ = 0.5. This increased the voltage gain by 12 dB, thus compensating for the gain loss introduced by the input capacitive divider (approximately 10 dB) while maintaining the overall circuit sensitivity to transistor mismatch at a relatively low level.

The second block creating the MIMO-DDTA is the multiple output transconductance amplifier. The circuit can be seen as a current-mirror linear OTA. Note that a version of the MI-TA with one positive output was presented and verified experimentally in [18]. Here, a second, inverting output has been added, thus increasing the circuit universality. Transistors M₁, M₂ and M₁₁, M₁₂ realize an input differential stage. The transistors M₁₁ and M₁₂ operate in a triode region and extend the linear range of the structure. The circuit can be seen as a BD version of the Krummenacher and Joehl transconductor [72], operating in weak inversion. Thanks to the BD approach, the linear range of the circuit is extended η = g_m1,2/g_mb1,2 times, as compared with its gate-driven (GD) counterpart. In order to obtain optimum linearity, the following condition should be met [18]:

$$k=\frac{{\left(W/L\right)}_{\mathrm{11,12}}}{{\left(W/L\right)}_{\mathrm{1,2}}}=0.5$$ (7)

where W and L are the MOS transistor channel width and length, respectively.

Assuming unity current gain of all current mirrors, the circuit transconductance is given by:

$$g_m=\eta \frac{4k}{4k+1}·\frac{I_{set}}{n_p{U}_T}$$ (8)

where n_p is the subthreshold slope factor, U_T is the thermal potential and I_set is the biasing current. Note that the circuit transconductance is proportional to this current.

In order to increase the DC voltage gain of the structure while not limiting its output voltage range, all current mirrors are based on self-cascode transistors. Consequently, the DC voltage gain from the input to the differential output is equal to:

$$A_{VO}\cong {2g}_m\left[\left(g_{m9}{r}_{ds9}{r}_{ds9c}\right)\right|\left|\left(g_{m6}{r}_{ds6}{r}_{ds6c}\right)\right]$$ (9)

Thanks to the self-cascode technique, it is possible to compensate for the gain loss associated with the application of the BD technique. In practice, a voltage gain of around 40 dB can be obtained.

3. Versatile Mixed-Mode Filter

Figure 4 shows the proposed versatile mixed-mode universal filter employing four MIMO-DDTAs and two grounded capacitors. Using (1) and nodal analysis, the output voltages V_o1, V_o2, V_o3 and the output currents I_o1, I_o2 can be given by:

$$V_{o1}=\frac{g_{m3}}{g_{m4}}·\frac{s^2{C}_1{C}_2\left(V_5-V_6\right)+{sC}_1{g}_{m2}\left(V_3-V_4\right)+g_{m1}{g}_{m2}\left(V_1-V_2\right)}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (10)

$$V_{o2}=\frac{s^2{C}_1{C}_2\left(V_5-V_6\right)+{sC}_1{g}_{m2}\left(V_3-V_4\right)+g_{m1}{g}_{m2}\left(V_1-V_2\right)}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (11)

$$V_{o3}=\frac{{sC}_2{g}_{m3}\left(V_5-V_6\right)+\left(s^2{C}_1{C}_2+{sC}_2{g}_{m3}\right)\left(V_3-V_4\right)+\left({sC}_2{g}_{m3}+g_{m1}{g}_{m3}\right)\left(V_1-V_2\right)}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (12)

$$I_{o1}=g_{m3}·\frac{s^2{C}_1{C}_2\left(V_5-V_6\right)+{sC}_1{g}_{m2}\left(V_3-V_4\right)+g_{m1}{g}_{m2}\left(V_1-V_2\right)}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (13)

$$I_{o1}=\frac{-s^2{C}_1{C}_2{I}_3{+sC}_1{g}_{m3}{I}_2-g_{m2}{g}_{m3}{I}_1}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (14)

$$I_{o2}=\frac{s^2{C}_1{C}_2{I}_3{-sC}_1{g}_{m3}{I}_2+g_{m2}{g}_{m3}{I}_1}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (15)

$$V_{o1}=\frac{1}{g_{m4}}·\frac{-s^2{C}_1{C}_2{I}_3{+sC}_1{g}_{m3}{I}_2-g_{m2}{g}_{m3}{I}_1}{s^2{C}_1{C}_2+{sC}_1{g}_{m3}+g_{m2}{g}_{m3}}$$ (16)

Figure 4.

The proposed versatile mixed-mode filter using MIMO-DDTAs.

From (10)–(16), the variant filtering functions can be determined and are shown in Table 1. The proposed mixed-mode universal filter can offer LP, HP, BP, BS, and AP filtering functions of VM, CM, TAM, and TIM in the same topology. Thanks to the multiple inputs of the DDTA, the VM, CM, and TIM can offer non-inverting and inverting transfer functions of LP, HP, BP, BS, and AP filters, and the VM and TAM can also offer differential transfer functions of LP, HP, BP, BS, and AP filters. Thus, the proposed mixed-mode filter can provide 61 transfer functions in a single topology. Thanks to the multiple outputs of the DDTA, such as DDTA₄, the proposed filter utilizes a minimum number of used DDTAs while offering inverting and non-inverting transfer functions of LP, HP, BP, BS, and AP filters of CM. The input signals V₁ to V₆ are connected to the high-impedance terminals of the DDTA; thus, the voltage signals can be applied without any buffer circuit requirements. The output signals V_o1 to V_o3 are connected to the low-impedance terminals of the DDTA, which offers a cascadable output for the voltage-mode filter structures. The output signals I_o1 and I_o2 are connected to the high-impedance terminals of the DDTA, which offers a cascadable output for the current-mode filter structures. However, in the case of CM, the inputs I₁ to I₃ require additional circuits, such as multiple-output current followers or multiple-output current mirrors, to create three identical current signals from the single original current signal. It is clear that the proposed filter is exempt from inverting-type input signal and input matching conditions for realizing all filtering functions both in the case of voltage and current signals.

Table 1.

Obtaining variant filtering functions of the proposed versatile mixed-mode filter.

Operation Mode	Filtering Function		Input	Output
VM	LP	Non-inverting	$V_1$	$V_{o1}$
		Inverting	$V_2$	$V_{o1}$
		Non-inverting	$V_1$	$V_{o2}$
		Inverting	$V_2$	$V_{o2}$
		Non-inverting	$V_1{=V}_6$	$V_{o3}$
		Inverting	$V_2{=V}_5$	$V_{o3}$
		Differential	$V_1{-V}_2$	$V_{o2}$
	BP	Non-inverting	$V_3$	$V_{o1}$
		Inverting	$V_4$	$V_{o1}$
		Non-inverting	$V_3$	$V_{o2}$
		Inverting	$V_4$	$V_{o2}$
		Non-inverting	$V_5$	$V_{o3}$
		Inverting	$V_6$	$V_{o3}$
		Differential	$V_3{-V}_4$	$V_{o2}$
	HP	Non-inverting	$V_5$	$V_{o1}$
		Inverting	$V_6$	$V_{o1}$
		Non-inverting	$V_5$	$V_{o2}$
		Inverting	$V_6$	$V_{o2}$
		Non-inverting	$V_3{=V}_6$	$V_{o3}$
		Inverting	$V_4{=V}_5$	$V_{o3}$
		Differential	$V_5{-V}_6$	$V_{o2}$
	BS	Non-inverting	$V_1{=V}_5$	$V_{o1}$
		Inverting	$V_2{=V}_6$	$V_{o1}$
		Non-inverting	$V_1{=V}_5$	$V_{o2}$
		Inverting	$V_2{=V}_6$	$V_{o2}$
		Differential	$\left(V_1{=V}_5\right)-\left(V_2{=V}_6\right)$	$V_{o2}$
	AP	Non-inverting	$V_1{=V}_4=V_5$	$V_{o1}$
		Inverting	$V_2{=V}_3=V_6$	$V_{o1}$
		Non-inverting	$V_1{=V}_4=V_5$	$V_{o2}$
		Inverting	$V_2{=V}_3=V_6$	$V_{o2}$
		Differential	$\left(V_1{=V}_4=V_5\right)-\left(V_2{=V}_3=V_6\right)$	$V_{o2}$
CM	LP	Non-inverting	$I_1$	$I_{o1}$
		Inverting	$I_1$	$I_{o2}$
	BP	Non-inverting	$I_2$	$I_{o2}$
		Inverting	$I_2$	$I_{o1}$
	HP	Non-inverting	$I_3$	$I_{o1}$
		Inverting	$I_3$	$I_{o2}$
	BS	Non-inverting	$I_1=I_3$	$I_{o1}$
		Inverting	$I_1=I_3$	$I_{o2}$
	AP	Non-inverting	$I_1=I_2=I_3$	$I_{o1}$
		Inverting	$I_1=I_2=I_3$	$I_{o2}$
TAM	LP	Non-inverting	$V_1$	$I_{o1}$
		Inverting	$V_2$	$I_{o1}$
		Differential	$V_1{-V}_2$	$I_{o1}$
	BP	Non-inverting	$V_3$	$I_{o1}$
		Inverting	$V_4$	$I_{o1}$
		Differential	$V_3{-V}_4$	$I_{o1}$
	HP	Non-inverting	$V_5$	$I_{o1}$
		Inverting	$V_6$	$I_{o1}$
		Differential	$V_5{-V}_6$	$I_{o1}$
	BS	Non-inverting	$V_1{=V}_5$	$I_{o1}$
		Inverting	$V_2{=V}_6$	$I_{o1}$
		Differential	$\left(V_1{=V}_5\right)-\left(V_2{=V}_6\right)$	$I_{o1}$
	AP	Non-inverting	$V_1{=V}_4=V_5$	$I_{o1}$
		Inverting	$V_2{=V}_3=V_6$	$I_{o1}$
		Differential	$\left(V_1{=V}_4=V_5\right)-\left(V_2{=V}_3=V_6\right)$	$I_{o1}$
TIM	LP	Non-inverting	$I_1$	$V_{o1}$
	BP	Inverting	$I_2$	$V_{o1}$
	HP	Non-inverting	$I_3$	$V_{o1}$
	BS	Non-inverting	$I_1=I_3$	$V_{o1}$
	AP	Non-inverting	$I_1=I_2=I_3$	$V_{o1}$

The voltage gain g_m3/g_m4 of the filtering functions can be obtained if the output V_o1 is used. In the case of TAM, the inputs V₁ to V₆ are converted to output currents by g_m3; in the case of TIM, the input currents I₁ to I₃ are converted to output voltages by g_m4.

The natural frequency (ω_o) and the quality factor (Q) can be given by:

$${\omega }_o=\sqrt{\frac{g_{m2}{g}_{m3}}{C_1{C}_2}}$$ (17)

$$Q=\sqrt{\frac{C_2{g}_{m2}}{C_1{g}_{m3}}}$$ (18)

It should be noted that the parameter ω_o can be controlled electronically by g_m2 and g_m3 and the parameter Q can be given by C₂/C₁.

Non-Ideality Analysis

Taking the tracking errors and the non-ideal transconductance of the MIMO-DDTA into account, the characteristics of the MIMO-DDTA can be rewritten as:

$$\left.\begin{array}{c}{V}_w={{\alpha }_{j+}V}_{y+1}+{\alpha }_{j+}{V}_{y+2}-{\alpha }_{j-}{V}_{y-}+{\alpha }_{j-}{V}_{y-2}\\ I_o=g_{mnj}{V}_w\end{array}\right\}$$ (19)

where α_j+ =1–ε_j+v and ε_j+v (|ε_j+v |≪ 1) denote the voltage tracking error from non-inverting terminals (i.e., V_y+1, V_y+2) to the w-terminal (i.e., V_w) of the j-th DDTA, α_j− =1–ε_j-v and ε_j-v (|ε_j-v|≪ 1) denote the voltage tracking error from inverting terminals (i.e., V_y−1, V_y−2) to the w-terminal (i.e., V_w) of the j-th DDTA, and g_mnj is the non-ideal transconductance gain of the j-th DDTA. The non-ideal transconductance g_mnj of the j-th DDTA at a frequency near the cut-off frequency can be expressed by [59]:

$$g_{mnj}\left(s\right)\cong g_{mj}\left(1-{\mu }_{j}s\right)$$ (20)

where μ_j= 1⁄ω_gmj, ω_gmj denotes the first pole frequency of the j-th g_m.

Using (19), the denominator of (10)–(16) can be modified as:

$$s^2{C}_1{C}_2+s{C}_1{g}_{mn3}{\alpha }_{3-}+g_{mn2}{g}_{mn3}{\alpha }_{2+}{\alpha }_{3-}$$ (21)

Using (20), (21) becomes:

$$\left\{s^2{C}_1{C}_2\left(1-\frac{C_1{g}_{m3}{\mu }_3{\alpha }_{3-}-{g_{m2}{g}_{m3}{\alpha }_{2+}{\alpha }_{3-}\mu }_2{\mu }_3}{C_1{C}_2}\right)+s{C}_1{g}_{m3}{\alpha }_{3-}\left(1-\frac{g_{m2}{g}_{m3}{\alpha }_{2+}{\alpha }_{3-}\left({\mu }_2+{\mu }_3\right)}{C_1{g}_{m3}{\alpha }_{3-}}\right)+g_{m2}{g}_{m3}{\alpha }_{2+}{\alpha }_{3-}\right\}$$ (22)

The tracking errors and the non-ideal effect of the transconductance of the DDTA can be made negligible by satisfying the following condition:

$$\left.\begin{array}{c}\frac{g_{m2}{g}_{m3}{\alpha }_{2+}{\alpha }_{3-}\left({\mu }_2+{\mu }_3\right)}{C_1{g}_{m3}{\alpha }_{3-}}\ll 1\\ \frac{C_1{g}_{m3}{\mu }_3{\alpha }_{3-}-{g_{m2}{g}_{m3}{\alpha }_{2+}{\alpha }_{3-}\mu }_2{\mu }_3}{C_1{C}_2}\ll 1\end{array}\right\}$$ (23)

The modified natural frequency (ω_on) and the modified quality factor (Q_n) can be expressed as:

$${\omega }_{on}=\sqrt{\frac{g_{m2}{g}_{m3}}{C_1{C}_2}·{\alpha }_{2+}{\alpha }_{3-}}$$ (24)

$$Q_n=\sqrt{\frac{C_2{g}_{m2}}{C_1{g}_{m3}}·\frac{{\alpha }_{2+}}{{\alpha }_{3-}}}$$ (25)

To consider the parasitic impedances that affect the proposed mixed-mode filter, the parasitic capacitance C_o and parasitic conductance g_o (g_o = 1/R_o, R_o is the output resistance) at the o-terminal of the DDTA are considered while the parasitic impedances at the y- and w-terminals are neglected. Considering Figure 4, the parasitic capacitances C_o1, C_o4 and parasitic conductances g_o1, g_o4 are parallel with C₁ and the parasitic capacitances C_o2, C_o4, and parasitic conductances g_o2, g_o4 are parallel with C₂. C_o1, C_o2, C_o4 are, respectively, the parasitic capacitances at the o-terminal of DDTA₁, DDTA₂, DDTA₄, and g_o1, g_o2, g_o4 are, respectively, the parasitic conductances at the o-terminal of DDTA₁, DDTA₂, DDTA₄. The parasitic capacitances can be neglected by appropriately choosing values such that C₁ ≫ C_o4 + C_o4, C₂ ≫ C_o2 + C_o4, g_m2 ≫ g_o1 + g_o4, and g_m3 ≫ g_o2 + g_o4.

4. Simulation Results

The circuit was designed and simulated using the Cadence Virtuoso System Design Platform using 0.18 µm CMOS technology from TSMC. The voltage supply was ±250 mV (0.5 V) and the bias voltage V_B1 = −100 mV. The transistor aspect ratios are included in Table 2. It is worth noting that the only increase in chip area is due to the input capacitor C_B = 0.5 pF, so the total input capacitance of the proposed MIMO-DDTA is 3 pF. This value is acceptable for integration.

Table 2.

Transistor aspect ratios of the MIMO-DDTA.

MI-DDA	W/L (µm/µm)
M1A, M2A, M1B, M2B M14, M15	16/3
M3–M8, M11–M12, MB	8/3
M9, M10	4/3
M16	6 × 16/3
M13	6 × 8/3
MR	4/5
MIM capacitor: CB = 0.5 pF, Cc = 6 pF
MO-TA	W/L (µm/µm)
M1, M2	2 × 15/1
M3–M6, M14–M16	2 × 10/1
M3c–M6c, M14c–M16c	10/1
M7–M10, M17–M19, M13	2 × 15/1
M7c–M10c, M17c–M19c, M13c, M11, M12	15/1

Selected simulation results for the MIMO-DDTA are shown in Figure 5 and Figure 6. Figure 5 shows the simulated results of the DC transfer characteristic of the MI-DDA V_w versus V_y+1 and of the MO-TA I_o+, I_o− versus V_w with various I_set. The extended linearity of operation despite the low supply voltage is observed.

Figure 5.

The DC transfer characteristics of the MIMO-DDTA: (a) V_w versus V_y+1 and (b) I_o+, I_o− (dashed line) versus V_w with various I_set.

Figure 6.

The impedances frequency characteristics of the MIMO-DDTA: (a) Z_y, Z_o+, Z_o− and (b) Z_W.

Figure 6 shows the impedances frequency characteristics of the MIMO-DDTA with I_set = 4 nA: (a) Z_y, Z_o+, Z_o− and (b) Z_W. At low frequency, the impedance of Z_y = 29.5 GΩ, Z_o+ =Z_o− = 2.1 GΩ and Z_w = 876 Ω. All these values are suitable for the proposed filter application.

For the filter application, for cutoff frequency 220 Hz and for I_set = 4 nA (g_m = 27.7 nS) the Equation (17) has been used to calculate the value of capacitors C₁ = C₂ = 20 pF. The frequency responses of the gain and phase for the differential input VM, non-inverting CM, TAM and TIM filter with I_set1–4 = 4 nA are shown in Figure 7. The simulated cutoff frequency was 211 Hz, which is closed to the calculated one. This slight deviation in the cutoff frequency can be easily corrected by adjusting the setting current. The power consumption of the filter was 281 nW.

Figure 7.

The frequency characteristics of gains for the VM (a), CM (b), TAM (c), and TIM (d).

The frequency responses of LP, HP, BP, BS, and AP gains and phases for VM are shown in Figure 8. The wide tunability of the filter is achieved by varying the setting current I_set1–4 = (0.5, 1, 2, 4) nA, where the cutoff frequency was (28, 56, 112, 211) Hz, respectively.

Figure 8.

The frequency characteristics of gains (lines) and phases (points) for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).

Monte Carlo (MC) analysis was used to perform the statistical analysis to estimate the parametric yield and generate information about the performance characteristics of the differential input VM filter. The gains frequency responses of LP, HP, BP, BS, and AP with 200 runs MC are shown in Figure 9. The curves are overlapping or close to each other.

Figure 9.

The 200 runs MC frequency characteristics of the gains for the differential input VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).

The process, voltage, and temperature (PVT) corners were also used to confirm the robustness of the design. The process transistor corners were fast–fast, fast–slow, slow–fast, and slow–slow. The process MIM capacitor corners were fast–fast and slow–slow. The voltage supply corners were = ±10% (V_DD-V_SS) and the temperature corners were −20 °C and 70 °C. The results for the gains frequency responses of LP, HP, BP, BS, and AP with PVT are shown in Figure 10. The curves are again overlapping or close to each other, which confirms the robustness of the filter design. In addition, thanks to the tunability of the filter, any deviation in the cutoff frequency can be easily adjusted by the setting current.

Figure 10.

The PVT frequency characteristics of the gains for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).

The transient response of the VM LPF with an applied input sinusoidal signal V_in-pp = 200 mV@10 Hz is shown in Figure 11a. The spectrum of the output signal is shown in Figure 11b, where the total harmonic distortion (THD) of 0.23% is indicated.

Figure 11.

The transient response of the VM LPF (a) and the spectrum of the output signal (b).

The THD for the VM LPF with different peak-to-peak input signal values @ 10 Hz is shown in Figure 12. The 1% THD is achieved for V_in-pp = 300 mV. The output voltage noise for the VM LPF is shown in Figure 13. The root-mean-square (RMS) output noise integrated in the bandwidth of 1 to 211 Hz was 130 μV; thus, the dynamic range (DR) of the VM LPF filter is 58.23 dB @ 1% THD.

Figure 12.

The THD of the VM LPF with different peak-to-peak input voltages @ 10 Hz.

Figure 13.

The output voltage noise of the VM LPF.

The proposed versatile mixed-mode filter was compared with the previously reported filters in [29,32,45,51,59,60,61] as shown in Table 3. Compared with these previous works, the proposed filter offers the most transfer functions of the five standard filtering functions and the lowest voltage supply. Compared with [29,32], the proposed filter offers electronic tuning capability of the natural frequency; compared with [59,60,61], the proposed filter uses fewer active devices. The filters in [32,45,51] apply the input signal via capacitor and/or resistor, the structure in [45] does not provide five standard filtering functions of VM, CM, TAM, and TIM, and the filters in [45,51] require input matching conditions for realizing some filtering functions.

Table 3.

Comparison of the proposed filter’s properties with those of mixed-mode universal filters.

Factor	Proposed	[29]	[32]	[45]	[51]	[59]	[60]	[61]
Number of active devices	4-DDTA	3-DDCC	1-FDCCII, 1-DDCC	2-VDBA	3-VDBA	5-OTA	8-OTA	5-DDTA
Realization	0.18 µm CMOS	0.25 µm CMOS	0.18 µm CMOS	0.18 µm CMOS	0.18 µm CMOS	0.18 µm CMOS	0.18 µm CMOS	0.18 µm CMOS
Number of passive devices	2-C	2-C, 3-R	2-C, 6-R	2-C, 2-R	2-C, 1-R	2-C	2-C	2-C
Type of filter	MIMO	MISO	MIMO	MIMO	MIMO	MISO	MIMO	MIMO
Total number of offered responses	61	30	36	17	20	20	20	36
Each mode offers five standard responses	Yes	Yes	Yes	No	Yes	Yes	Yes	Yes
Orthogonal control of ${\omega }_o$ and $Q$	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Electronic control of ${\omega }_o$	Yes	No	No	Yes	Yes	Yes	Yes	Yes
All passive devices grounded	Yes	Yes	No	No	No	Yes	Yes	Yes
High input impedances for VM	Yes	Yes	No	No	No	Yes	Yes	Yes
No need for input matching conditions	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes
No need for inverting input conditions	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Power supply (V)	0.5	±1.25	±0.9	±0.75	±1.25	±0.9	±0.3	1.2
Power dissipation (mW)	0.281 × 10−3	-	-	0.373	5.482	0.1773	0.00577	0.33
Natural frequency (kHz)	0.211	3.315 × 103	1.591 × 103	1.44 × 103	16.32 × 103	3.39 × 103	5	1.04
Total harmonic distortion (%)	1@300 mVpp (LPF)	0.723@60 µApp	2.2@300 mVpp	2.2@200 mVpp	<4@350 mVpp (HPF)	-	2@120 mVpp (LPF)	1.09@650 mVpp
Dynamic range (dB)	58.23	-	-	-	-	-	53.2	-
Verification of result	Sim	Sim	Sim	Sim/Exp	Sim/Exp	Sim	Sim	Sim/Exp

Note: MIMO = multiple-input multiple-output, MISO = multiple-input single-output.

5. Conclusions

This paper presents a 0.5 V, 281 nW versatile mixed-mode universal filter using MIMO-DDTAs. The MIMO-DDTA is used to realize a versatile mixed-mode universal filter that offers many transfer functions in the same topology. To realize variant transfer functions such as LPF, HPF, BPF, BSF, and APF of VM, CM, TAM, and TIM, inverted input signal requirement is absent. The natural frequency can be electronically controlled. The VM filter offers high-input impedance and low-output impedance, and the CM filter offers high-output impedance. For the VM LP filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm CMOS technology from TSMC. The simulation results, including Monte-Carlo and PVT corners, confirm the functionality of the design.

Author Contributions

Conceptualization, F.K., M.K. and T.K.; methodology, M.K. and F.K.; software, F.K.; validation, F.K. and T.K.; formal analysis, T.K., M.K. and F.K., investigation, F.K. and M.K.; resources, F.K. and M.K.; writing—original draft preparation, M.K., F.K. and T.K.; writing—review and editing, F.K. and T.K.; visualization, F.K., T.K. and M.K.; supervision, F.K.; project administration, F.K.; funding acquisition, F.K. and M.K. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflict of interest.

Funding Statement

This work was supported by the University of Defence within the Organization Development Project VAROPS.