Ag-doped non–imperfection-enabled uniform memristive neuromorphic device based on van der Waals indium phosphorus sulfide

Abstract

Memristors are considered promising energy-efficient artificial intelligence hardware, which can eliminate the von Neumann bottleneck by parallel in-memory computing. The common imperfection-enabled memristors are plagued with critical variability issues impeding their commercialization. Reported approaches to reduce the variability usually sacrifice other performances, e.g., small on/off ratios and high operation currents. Here, we demonstrate an unconventional Ag-doped nonimperfection diffusion channel–enabled memristor in van der Waals indium phosphorus sulfide, which can combine ultralow variabilities with desirable metrics. We achieve operation voltage, resistance, and on/off ratio variations down to 3.8, 2.3, and 6.9% at their extreme values of 0.2 V, 10¹¹ ohms, and 10⁸, respectively. Meanwhile, the operation current can be pushed from 1 nA to 1 pA at the scalability limit of 6 nm after Ag doping. Fourteen Boolean logic functions and convolutional image processing are successfully implemented by the memristors, manifesting the potential for logic-in-memory devices and efficient non–von Neumann accelerators.

An Ag-doped nonimperfection strategy can confine filament to combine ultralow variabilities with desirable switching parameters.

INTRODUCTION

With the approaching limits of Moore’s law, new efficient computational devices and architectures are required to sustain the growth of machine learning and artificial intelligence (AI) (1, 2). Memristors are highlighted as holding potential for energy-efficient AI hardware since they can colocate computation and memory in a single device, and their crossbar array architectures can provide large parallelism for matrix multiplication operations, which is the key computation in most AI models (2, 3). The memristors that rely on the formation/rupture of conductive filaments (CFs) have been the mainstream and are the most likely to be cosmically commercialized, considering their advantages in the high switching speed, low operation voltage, low power consumption, and high integration density (4). However, the uncontrolled ion transport imposes severe intrinsic variability of the resistive switching (RS) process, which has been one of the most critical issues that impede their commercialization (5, 6).

In general, the RS behavior is enabled by the imperfections in most memristors. Lattice vacancies and grain boundaries are the most common imperfections, which can directly form the CFs or provide the ion diffusion channel (5, 7). These imperfections are usually randomly distributed and form disordered ion diffusion channels, which should be the essential reason for the nonuniform and inconsistent RS. The low operation voltage (below 0.2 V), small leakage current (<10⁻¹² A), low nonvolatile operation current (picoampere-level), high on/off ratio, ultrathin RS media (below 10 nm), and other characteristics are desirable for high energy efficiency and scalability. However, at these extreme values, the switching variability will be more severely affected by the disordered defects, which makes it difficult to combine the low variability with these excellent performances (7–16). Approaches involving double-layered structures, heterophase grain boundaries, and dopants have been developed. These approaches aim to confine the formation of the CFs with the goal of improving switching uniformity (16–21). However, these approaches, which induce residual filaments or produce abundant defects around the dopant, usually lead to an obvious increase in conductance at the expense of the limited on/off ratio and operation current. Constructing homogeneous ion diffusion channels should be the more fundamental solution for uniform RS. However, it has been a challenge to fabricate by naturally random imperfections. Further seeking effective strategies is necessary to overcome the variability bottleneck without sacrificing other performances.

Here, we demonstrate an Ag-doped nonimperfection ion diffusion channel–enabled memristive switching, which can address the variability issues and achieve many desirable metrics. Unlike the common imperfection ion channel, the inherent periodic structural vacancies in van der Waals In_3/4P₂S₆ (IPS) serve as the ordered low-energy ion diffusion channel (22–24). Further using Ag preoccupied structural vacancies instead of the common lattice substitutions to confine the diffusion path, we can achieve low variabilities of 3.8, 2.3, and 6.9% for the low operation voltage (~0.2 V), high off-state resistance (~10¹¹ ohms), and big on/off ratio (~10⁸), respectively. Even for the extremely low operation voltage of 0.05 V, the variability can be down to 7.5%. Apart from the uniformity improvement, Ag doping can remarkably reduce the operation current to 1 pA at the scalability limit of 6 nm, which is two orders lower than that of the undoped IPS memristor with a similar thickness. Our strategy can remarkably improve uniformity without sacrificing other performances. On the basis of the well-rounded performance, 14 basic Boolean logic functions are realized. Furthermore, by leveraging on the crossbar array with high yield, kernels with varied sizes and parallel convolutional operation are implemented for multiple image processing tasks and manifest the potential for the development of non–von Neumann hardware. Such excellent performances are superior to state-of-the-art metal oxide and two-dimensional (2D) material–based memristors.

RESULTS

Enhanced RS uniformity in the Ag-IPS memristor

In contrast to the common metal phosphorus trichalcogenides with close-packed structures (such as Ni₂P₂S₆ and Mn₂P₂S₆), only four-third metal sites are occupied by indium (In), leaving two-third sites vacant in In_4/3P₂S₆ (IPS), i.e., the structural vacancies as illustrated in Fig. 1A (22). Unlike the usual disordered imperfection (such as lattice vacancies and grain boundaries), these structural vacancies (nonimperfection) are periodically arranged. When combined with its AAA stack structure, they form ordered vacancy channels and serve as the shortest ion diffusion pathway. In principle, these structural channels in perfect IPS are identical, which will lead to identical filaments via any channel. Thus, a uniform RS behavior during the repeated cycles can be expected. However, mediocre uniformities are observed in the Ag/IPS (~40 nm)/Au memristor (the structure is illustrated in fig. S1). As shown in Fig. 1 (B and C), the set and reset voltages of the IPS memristor are 0.24 to 0.64 V and −0.12 to −0.3 V, respectively, which results in mean set and reset voltages of 0.43 and −0.21 V and variations of 20.7 and −21.4%, respectively. Such variations show intermediate levels among the reported 2D materials and metal oxide–based memristors, as displayed in Fig. 1D and fig. S3, which indicates obvious variations in RS parameters. The unexpected discrepancies are due to the inevitable random distributed lattice vacancies [especially the sulfur (S) vacancies at the edge of the structural vacancy (i.e., V_S1)], which makes the ordered vacancy channel inconsistent, as schematically shown in Fig. 1 (A and E).

Fig. 1. Uniform RS in the Ag-IPS memristor.

(A) Atomic structure of monolayer IPS showing the intrinsic structural and lattice vacancies. (B and C) I-V curves during 100 cycles and the corresponding histogram of the set and reset voltage distributions of IPS (~40 nm) memristor. (D) Comparison of the set voltage variation among IPS, Ag-IPS, and reported 2D material– and oxide-based memristors. (E and F) Perspective view from the c axis of multilayer (E) pristine undoped IPS showing intrinsic structural channels with lattice defects and (F) Ag-doped IPS with the intrinsic vacancy occupied by Ag. (G and H) I-V curves during 100 cycles and the corresponding histogram of the set and reset voltage distributions of Ag-IPS (~40 nm) memristor. (I) Resistance and on/off ratio versus DC endurance cycles of the Ag-IPS device. (J) Variation comparison of the HRS resistance among the Ag-IPS and oxide-based memristors. The 2D material–based memristors are not shown here because there are rare articles reporting C_v of the resistances. Our Ag-IPS memristor has ultrahigh HRS resistance and the lowest variability. (K and L) Radar graph comparing the device metrics of the Ag-IPS memristor with (K) oxide- and (L) 2D material–based memristors. Our device shows the best overall performance. C_V, coefficient of variation; C_V = σ/μ, where σ and μ are the SD and mean value of the resistance, respectively. For detailed references, please see tables S1 and S2 [marked in blue for (D), marked in green for (J), and marked in purple for (K) and (L)]. Before the repeated I-V cycles, electroforming processes are required (fig. S2). The size of the IPS and Ag-IPS memristors is 2 × 2 μm².

Impressively, when the structural vacancies are partially presubstituted by Ag (Ag-IPS), as schematically displayed in Fig. 1F, the uniformities of RS parameters are dramatically improved. As shown in Fig. 1 (G and H), the memristor integrated with Ag-IPS (~40 nm) exhibits an extremely uniform bipolar nonvolatile RS behavior with set voltage and reset voltage variations of 3.8 and −9.4%, respectively. Such uniformity and the low operation voltages almost stand alone in the region of the operation voltage <0.3 V and variation <10%, as presented in Fig. 1 (D and H) and fig. S3. The enhanced uniformity can also be found in thinner samples, as shown in fig. S4. Compared with the operation voltages, fewer articles are devoted to improving the uniformity of resistances, as shown in tables S1 and S2. Resistance states with small variations are crucial for high computing accuracy and efficiency, since they represent the weights in computing (3). A large resistance in the high-resistance state (HRS) is advantageous for reducing power consumption, eliminating sneak current, lowering operational current, and achieving a high on/off ratio for numerous conductance levels. The resistance in HRS is usually more prone to fluctuate than that in the low-resistance state (LRS), since the current in HRS flows across a random number of defects along the total RS media, whereas the current in LRS flows along the CFs (6). The Ag-IPS memristor has a lower mean HRS resistance than the IPS sample, as shown in fig. S5. However, it retains a high value of approximately 10¹¹ ohms, contributing to a high on/off ratio up to 10⁸. The resistances demonstrate small variations and good cyclical endurance, where the resistance variations of LRS and HRS over 1000 DC cycles are down to 5.8 and 2.3%, respectively (Fig. 1I). Such low variation at high HRS resistance has occupied the most prominent position among oxide-based memristors, as presented in Fig. 1J. Simultaneously, the small variations in resistance maintain the on/off ratio at 10⁸ with a low dynamic range of 6.9% over 1000 DC switching cycles, as exhibited in Fig. 1I. This value is in contrast to other memristors, where uniformity is achieved but with a small on/off ratio (19, 25–27). Good endurance is also achieved using pulses, as the device can normally be SET/RESET with more than 10⁴ switching cycles, as exhibited in fig. S6. Performance bench markings (Fig. 1, K and L) further show that the Ag-IPS memristor can achieve ultralow variabilities of RS parameters at extremely low operation voltages, high HRS resistance, and large on/off ratios, which are notable among the oxide- and 2D material–based nonvolatile memristors. These results indicate that using Ag doping IPS is a superior strategy for excellent uniformity.

The fast development of machine learning techniques and the rapid increase in scale of artificial neural networks place demands on the underlying electronic hardware, particularly their energy consumption (2). A memristor with a low operation current is essential to reduce energy consumption. The operation currents for nonvolatile RS of the thick IPS memristor (~40 nm) can reach an ultralow value of 1 pA. However, the low operation current cannot be maintained in its thin samples, and it will increase notably to 1 nA for a thickness of 8 nm, as shown in Fig. 2 (A to C). In contrast, the ultralow operation current can be achieved regardless of the thickness in Ag-IPS devices, where the scalability limit can be pushed to 6 nm with a 1-pA-level operation current (see Fig. 2, D to F). Moreover, the nonvolatile RS under low operation currents of 1 and 10 pA are reproductive and uniform, as shown in Fig. 2 (G and H). Meanwhile, the Ag-IPS memristor exhibits a good retention performance, lasting longer than 10⁵ s without obvious degradation under different operation currents at room temperature (Fig. 2J). With the exception of the operation current of 1 pA at 350 K, the resistance states also show good retention under low (250 K) and high temperatures (350 K), as presented in fig. S7. These results confirm the ability of Ag-IPS memristors to operate in the nonvolatile style under ultralow operation currents. The high HRS resistance and low operation current result in the on/off ratio and nonvolatile on/off ratio of up to 10⁹ and 10⁸, as marked in red and blue dashed lines, respectively, in Fig. 2E. Attributing to this wide resistance range, which is advantageous to accommodate a large number of resistance states, 32 states with small fluctuations are obtained using operation currents from 1 pA to 1 mA, as shown in fig. S8. The achievement of multiple resistance states with good retention is a key performance metric for building artificial neural networks with multi-states/weights for various applications.

Fig. 2. Ultralow operation current and ultrahigh on/off ratio in the Ag-IPS memristors.

(A to F) Nonvolatile RS under different operation currents in (A to C) IPS memristors and (D to F) Ag-IPS memristors with different thicknesses. The red and blue curves mark the volatile RS and nonvolatile RS, respectively. All devices have a size of 2 × 2 μm². (G to I) Repeated RS in Ag-IPS memristors at low operation currents of (G) 1 pA and (H) 10 pA, along with (I) the corresponding distribution of the operation voltage. (J) Retention property of the Ag-IPS memristor under different operation currents (read at 0.05 V). (K) Benchmark plot comparing the operation current and on/off ratio among the Ag-IPS, 2D material–based, and oxide-based memristors. Most reported memristors have microampere-level operation currents and on/off ratios below 10⁶. The Ag-IPS memristor stands out with the highest on/off ratio (>10⁹) and lowest operation current of 1 pA. For detailed references, please see tables S1 and S2 (marked in yellow).

Moreover, the thin Ag-IPS memristor (6 nm) provides an exceptionally low operation voltage of 0.05 V with a concentrated distribution of 7.5%, as presented in Fig. 2I. This is in contrast to the reported memristors that have a low operation voltage but a large variability or those with a small variation but a large operation voltage (8, 10, 18, 28, 29). Low operation voltages and operation currents are beneficial to low power consumption. As shown in fig. S9, the Ag-IPS memristor can be switched on either by a pulse train with a width of 200 ns and an amplitude of 1.3 V or by a single pulse with a width of 100 ns and an amplitude of 2.8 V (the pulse width is determined by the full width at half maximum), which is confirmed by the DC sweepings (fig. S9, B and E) and the retention tests (fig. S9, C and F). A low energy consumption of approximately 18.5 fJ per spike is achieved with a short switching time of 100 ns. A performance benchmarking in Fig. 2K shows that our Ag-IPS memristor with an operation current of 1 pA and an on/off ratio of 10⁹ occupies the uninhabited region. In summary, the Ag-IPS memristor has many outstanding metrics, including the nonvolatile operation current of 1 pA, maximal on-off ratio of 10⁹, sub–0.1 V operation voltage, femtojoule-level power consumption, and low variability of 2.3%. These values highlight that the Ag-IPS memristor is a promising candidate for high-efficiency AI hardware.

RS mechanism of Ag-IPS memristor

The mechanism of the Ag doping–induced RS uniformity and low programming current are explored. The pristine exfoliated IPS, with an In:P:S ratio of 2:2.6:7.6, contains some P and S vacancies, as shown in fig. S10. The structure and composition of Ag-IPS are studied using the scanning transmission electron microscopy–annular dark field (STEM-ADF) and energy-dispersive x-ray spectroscopy (EDS) elemental mapping. The Ag-IPS nanosheet displays fine lattice fringes with the interplanar d-spacing of 0.178 nm and hexagonally arranged selected-area electron diffraction (SAED) spots recorded from the [001] zone axis (Fig. 3A, top), which inherits the structure of the single-crystalline IPS. A small amount of element Ag is detected in both EDS mapping and x-ray photoelectron spectroscopy (XPS) spectra in the Ag-IPS sample, as shown in Fig. 3A (bottom) and fig. S11, respectively. The atomic ratios of Ag:In:P:S calculated from the EDS and XPS data are 0.07:2:2.6:7.6 and 0.1:2:2.2:4.6, respectively, which confirms a low Ag doping and the existence of P and S vacancies. The doping is also evidenced by the ultraviolet (UV)–visible absorption spectra in Fig. 3B, where the measured bandgap is narrower than that of the pristine IPS. First-principles theory [density functional theory (DFT)] calculations reveal that Ag prefers to occupy the intrinsic structural vacancies in IPS since they show the lowest formation energy compared to the P and S vacancies (fig. S12). This behavior results in n-type doping, where the Ag doping contributes electron to the IPS and induces near-edge states that make the Fermi level enter the conduction band, as shown in fig. S13. The extra electrons donated by dopants can be verified by the photoluminescence enhancement effect, in which an obvious broad asymmetric peak is observed in the Ag-IPS sample (Fig. 3C) (30). Further calculation of the differential charge density distribution reveals the charge transport between the Ag atom and the surrounded atoms, where Ag donates electrons to the surrounded atoms, as shown in Fig. 3D. Thus, the vacancy site around the Ag dopant with nonequilibrium carriers becomes more charged than the vacancies farther from the doped Ag, as illustrated in Fig. 3D. In other words, the Ag doping forms a charged structural vacancy channel around Ag.

Fig. 3. RS mechanism.

(A) Top-view scanning STEM-ADF (top left) with the corresponding SAED image (top right) and EDS mapping (bottom) of Ag-IPS. The scale bar of the SAED image is 5 1/nm. (B) Micro–UV-visible absorption of the pristine IPS and Ag-IPS. The Ag-IPS has a smaller bandgap than the IPS. (C) Photoluminescence (PL) spectra of IPS and Ag-IPS under a 532-nm laser. (D) Differential charge density distribution of Ag-IPS. The differential charge density is calculated by subtracting the pristine IPS charge density from the Ag-IPS charge density. The lake blue and dusty blue isosurface contours represent the charge accumulation and depletion, respectively. (E) Calculated diffusion energy barriers of Ag migrating through adjacent layers via the structural vacancy (V_int.) and S vacancy (V_S1) in the IPS and via charged vacancies around the doped Ag in Ag-IPS. (F) Schematic illustration of the concentrated CF formation in the Ag-IPS memristor.

We confirm that the electrochemical metallization mechanism (ECM) is the dominant mechanism in the Ag-IPS memristor since obvious Ag migration and the formation of CFs are observed using cross-sectional high-resolution TEM (HR-TEM; fig. S14) and EDS analysis (fig. S15) in the Ag-IPS memristor. When inert Pd instead of Ag is used as the top electrode, no RS behavior is observed (fig. S16), which indicates that the Ag active ions from the electrode contribute to the formation of CFs instead of the dopant Ag. The structural vacancy channel should be the most desirable filament formation path since the diffusion barrier is lower than that via the S vacancy (see Fig. 3E). There are disordered P and especially S vacancies located beside the structural vacancy, which make the theoretical homogeneous vacancy channels inconsistent and result in variabilities of RS parameters in pristine IPS memristors. When Ag preoccupies the structural vacancy, electrons are donated and induce charged structural vacancies in the surroundings. The DFT calculation reveals that the diffusion barrier of Ag migrating through adjacent layers via the charged structural vacancy near the Ag dopant (0.1433 eV) is much lower than that via the pristine vacancies (0.3279 eV), which indicates a more energetic ion diffusion path around the doped Ag, as shown in Fig. 3E. Figure S17 illustrates the corresponding diffusion pathway. As a consequence, concentrated ion transport is achieved, and the filament formation path is confined around the doping Ag, as schematically illustrated in Fig. 3F, which results in an extremely uniform RS behavior in the Ag-IPS device. The post-formed Ag resulting from electrode oxidation differs from the pre-doped Ag, as it cannot induce a uniform RS behavior (note S1 and fig. S18). Meanwhile, the concentrated formation path can enhance the stability of the filament, leading to the achievement of an ultralow operation current in thin Ag-IPS samples, as discussed in note S2 and fig. S19. Moreover, the much lower diffusion barrier explains the lower operation voltages in the Ag-IPS memristor than those in the pristine IPS memristor. In addition, because of the low Ag doping, the HRS resistance of the Ag-IPS memristor shows only a limited decrease compared to its intrinsic sample. Therefore, the Ag-IPS memristor maintains a large resistance and on/off ratio (fig. S5 and note S2). In summary, the Ag-doped nonimperfection diffusion channel can provide an ultralow energy diffusion pathway that can confine the formation pathway and stabilize the filaments, which leads to a remarkably uniform RS switching with low operation current and operation voltage at the scalability limit.

Experimental demonstration of logic-in-memory computing

Memristors that can directly implement logic functions in a single device will reduce the hardware and materials footprint (1, 31). Here, we demonstrate that the Ag-IPS memristor holds great potential for reliable Boolean logic computation. Through three steps (initialization, operation, and readout), any single device can conduct the required logic function (31). Logic terms such as logic variables p and q, terminals In1 and In2, and logic values “0” and “1” are introduced into the system. The logic variables p and q are assumed to be 0 or 1, which correspond to voltage levels applied to the junction terminals In1 and In2. The terminals In1 and In2 can be 0 or 1, where 0 represents the low potential and 1 represents the high potential. The top Ag electrode and bottom Au electrode are assigned to In1 and In2, respectively. The logic operation In1In2 includes 00, 01, 10, and 11. According to the logic operation, the voltage biases are simultaneously applied to the top and bottom electrodes. For example, when the combination of In1In2 is 01, the voltage biases of 0 and 2 V are applied to the top and bottom electrodes, respectively. The device in the HRS represents the state of 0, and the LRS represents the state of 1. Figure 4A shows the corresponding operation schematic.

Fig. 4. Experimental demonstration of Boolean logic operations in the Ag-IPS memristor.

(A) Logic operations by a single device. The top (Ag) and bottom (Au) electrodes of the device are marked with In1 and In2, where logic operations In1In2 include 00, 01, 10, and 11. Here, 0 represents a low potential (0 V) and 1 represents a high potential (2 V). For example, 01 means applying 0 and 2 V to the terminals In1 and In2, respectively. (B) The truth tables show the operation sequence to the logic function p NIMP q. (C to J) Experimental demonstration of the p NIMP q logic operation and the corresponding distribution of the output current and initial current opposite to the output logic. For example, the current of state 0 in (G) is extracted from the output current after logic operations in (C), while the opposite logic, i.e., state 1, is obtained from the initialization step. The output currents of the four experiments are clearly distinguished from each opposite logic current. (K) The truth table of 14 fundamental Boolean logic functions was obtained from our experiments.

The implementation of material nonimplication (NIMP) was taken as an example to verify the logic-in-memory ability of our device. The corresponding truth table of logic NIMP is shown in Fig. 4B. First, an initial characterization operation was performed before the logic operations to initialize the device to the HRS state and check whether the device could be correctly SET and RESET by the pulse bias voltages, as shown in the “initialization” regime of Fig. 4C. The logic operation can also be performed without initialization, as shown in fig. S22. However, the initialization step that can define states 0 and 1 is beneficial to quickly check the output state (0 or 1) after the logic operations and confirm the logic reliability by comparing the output current and initial current of the opposite logic. Subsequently, pulse bias voltage sequences designed according to the truth table (see Fig. 4B) were applied to the device to conduct the logic operation. Last, a readout operation (0.1 V) was performed to read the output current, i.e., the logic value. As shown in Fig. 4 (C to F), the states 0 and 1 were clearly distinguished and defined in the initialization step, and the output logic values were quickly confirmed according to the defined 0 and 1. Moreover, the ratio of the output logic current/opposite logic current is larger than 100 for all four logic experiments, which indicates the reliable logic computation of NIMP, as shown in Fig. 4 (G to J). Therefore, we have experimentally demonstrated the successful implementation of the NIMP logic function using eight pulse sequences in our device. By executing different pulse schemes, the other 13 fundamental Boolean logic functions in Fig. 4K, including material implication (IMP), Not, NOR, and NAND, can be experimentally realized using our device (see fig. S21). In addition, a simplified method can perform the logic operations, where only the top electrode is used to apply the voltage bias and the bottom electrode is grounded, as schematically shown in fig. S20B. Consequently, when the combinations of In1In2 are 00, 01, 10, and 11, the voltage biases of 0, −2, 2, and 0 V are applied to the top electrode, respectively. Figure S23 shows the corresponding operation results. The results indicate the potential of our device as logic-in-memory computing hardware.

Convolutional image processing

The Ag-IPS memristor crossbar array with high yield was further fabricated. Figure 5A shows a 10 × 8 memristor crossbar array, where all devices present nonvolatile RS under operation currents from 100 pA to 100 μA (see fig. S24). Five states (HRS, LRS1, LRS2, LRS3, and LRS4) using operation currents of 100 pA, 10 nA, 1 μA, and 100 μA show good spatial uniformity, as shown in Fig. 5B. These states can be reliably distinguished without overlap, and the on/off ratios of HRS/LRS1 to LRS4 are at least 10, 10³, 10⁵, and 5 × 10⁷ for each operation current, respectively, as shown in fig. S25 and Fig. 5C.

Fig. 5. Convolutional image processing using the Ag-IPS memristor crossbar array.

(A) Optical image of a 10 × 8 Ag-IPS memristor crossbar array; the device size is 2 × 2 μm². (B) The conductance distributions correspond to the five states (HRS and LRS1 to LRS4). The four LRS states are obtained using different operation currents of 100 pA, 10 nA, 1 μA, and 100 μA. The conductance data are extracted from the I-V curves in fig. S24. (C) Cumulative probability plots of the on/off ratio in different LRS states over 80 devices in the Ag-IPS crossbar array. (D) Comparison of the convolutional image processing of edge embossment with different kennel sizes. The 10 × 8 Ag-IPS memristor crossbar array can implement 3 × 3, 5 × 5, and 7 × 7 kernels for different image processing applications. (E) Parallel convolutional image processing of four feature maps implemented by the Ag-IPS memristor crossbar array.

Convolutional neural networks (CNNs) have been one of the most important models for image recognition, where image processing (or feature extraction) is the basic and most frequently used operation. Convolutional kernels in different sizes can extract different feature information. The small-size kernel can extract the local texture feature information, and the large-size kernel can extract the global contour feature information (32). Using or combining different kernels with varied sizes can obtain different image processing effects for various applications. Here, by leveraging the Ag-IPS memristor crossbar array structure and the corresponding measured conductance (G) data in Fig. 5B, we constructed convolutional kernels with different sizes. Specifically, two memristors were used as a differential pair to represent both positive and negative weight values. Then, the weights of −1/+1 were mapped by the HRS and LRS, i.e., G^HRS − G^LRS1/2/3/4 ~ −1, and G^LRS1/2/3/4 − G^HRS ~ +1. Consequently, two 3 × 3 (or 5 × 5 or 7 × 7) crossbar arrays were used to construct the target 3 × 3 (or 5 × 5 or 7 × 7) G convolution kernel (33), where the conductance values were obtained from the conductance map (Fig. 5B) according to the position and resistive state (HRS, LRS1, LRS2, LRS3, or LRS4) of the memristor, as illustrated in fig. S26. The building of Wuhan University (WHU building) was used as the input image, and the image intensity was converted into voltages, as illustrated in fig. S26A (16). Subsequently, the convolution of the input voltage matrix and G convolution kernel was implemented, i.e., I_out = V_ij * G_ij. Here, I_out is the sum of differential currents, i.e., $I_{\text{out}}=\sum (I_j^{+}-I_{j+3}^{-})$ . Last, I_out was converted into the pixel. The complete image processing was achieved by conducting the convolution operations over the entire image. G convolution kernels were mapped from the conductance of the actual devices in the crossbar array, whereas the convolutional operation was simulated using the software code. Figure 5D and fig. S27 show the image processing of embossment and mean softening using varied convolutional kernels, respectively. As displayed in Fig. 5D, the smaller convolution kernel pays more attention to the details of the image (local texture), e.g., both thick and thin branches are highlighted when a 3 × 3 kernel is used. When the size of the convolution kernel increases, the global contour feature of the WHU building is enhanced with some loss in local texture (thin branches become unobvious). Similarly, the softening effect is enhanced when the kernel size increases, as displayed in fig. S27. Therefore, the convolutional kernels with varied sizes were successfully constructed using our Ag-IPS memristor array, and the impact of kernel sizes on image processing is well presented.

In the above image processing scheme, the voltages should be applied column by column. A more efficient parallel convolutional image processing is further demonstrated using the Ag-IPS memristor crossbar array, as shown in Fig. 5E and fig. S28. Here, the 3 × 3 input voltage matrix was unrolled into one column, i.e., 9 × 1. A two-column array of 9 × 2 instead of 3 × 3 × 2 was used to implement the 3 × 3 convolutional kernel, where one column represents the sum of the products of the positive values in the filter (I⁺), and the other column represents the sum of the products of the negative values in the filter (I⁻) (33). Consequently, a differential readout of the two-column currents (I⁺ − I⁻) is the convolution output. Using the entire 9 × 8 size of the array, four different G convolution kernels for vertical and horizontal edge extraction, edge embossment, and mean soften were simultaneously built. Similarly, the G convolutional kernels were constructed using the measured conductance data of the memristors, and fig. S28A shows the conductance map that corresponds to the target convolution kernel. The product and summation of V_i and G_ij, i.e., $I_j^{+}$ or $I_j^{-}$ = ΣV_i × G_ij, the sum of differential currents representing the convolutional output, i.e., $I_{\text{outj}}=I_j^{+}-I_j^{-}$ , and the final operation of converting I_out into image pixel were performed using the software code. With this strategy, four different image processing actions can be simultaneously conducted, as illustrated in Fig. 5E and fig. S28A. The yellow crane tower was used as the input image. The image was successfully softened after the convolution operation, where the pixel distribution was similar to the original one but slightly adjusted [Fig. 5E (II) and fig. S28B]. The vertical and horizontal edges of the yellow crane tower were extracted, where the pixel intensity was concentrated in a narrow range, as presented in Fig. 5E (III and IV) and fig. S28 (C and D). Meanwhile, the relief effect of the yellow crane tower was realized by edge embossment processing with a shrunken pixel distribution, as exhibited in Fig. 5E (V) and fig. S28E. These results indicate that the parallel processing of four feature maps was achieved. In summary, the Ag-IPS memristor crossbar array can implement convolution kernels with varied sizes for different image processing actions, which manifests its potential as the building block for CNNs.

DISCUSSION

In this study, we demonstrated that using Ag-doped inherent vacancy channel of IPS can facilitate a low-energy ion diffusion pathway to confine the filament formation. Attributed to the confinement, the Ag-IPS memristor achieves ultralow variabilities of RS parameters at extreme values. At a low operation voltage of 0.2 V, the variation is as low as 3.8%. Similarly, the high resistance at 10¹¹ ohms exhibits a variation down to 2.3%, and a large on/off ratio of 10⁸ shows a small variation of 6.9%. Moreover, the ultralow operation current of 1 pA, femtojoule-level switching energy, and high-yield memristor crossbar array are also obtained. On the basis of the developed memristors, the 14 Boolean logic functions are experimentally implemented. Leveraging its crossbar array with high yield and uniform states, convolution kernels with varied sizes and parallel convolution operations for multiple image processing tasks are successfully performed. We provide an unconventional strategy for superior in-memory computing hardware, which can combine low variabilities with excellent RS parameters.

MATERIALS AND METHODS

Device fabrication

The IPS and Ag-doped IPS crystals were synthesized by chemical vapor transport by Six Carbon Technologies Inc. The bottom electrode by depositing a layer of Cr/Au (5/20 nm) onto a 300-nm silicon dioxide substrate is first fabricated through an e-beam-thermal evaporator system. Then, the IPS or Ag-doped IPS nanosheets with different thicknesses were exfoliated and transferred onto the bottom electrode. Last, the devices were finished by depositing an Ag/Au (40/40 nm) as the top electrode. Both the top and bottom electrodes were patterned by UV lithography using AZ5214 as the photoresist. The size of both IPS and Ag-IPS devices is 2 × 2 μm².

Device measurement

A B1500 semiconductor parameter analyzer equipped with a probe station (Lakeshore, TTP4) is used to measure the I-V characteristics of the memristors. The Ag electrode was used as the top electrode to apply bias voltage, and the Au electrode was used as the bottom electrode and grounded. The pulse measurement is performed using an SCS-4200 semiconductor parameter analyzer equipped with a probe station (Lakeshore, TTP4).

Material characterization

The top-view atomic resolution STEM-ADF and EDS elemental mapping were conducted in JEM-ARM200CF (80 kV). The cross-sectional HR-TEM was performed in JEM-NEOARM (200 kV). X-ray photoelectron spectra were measured using a Quantera PHI II system with a monochromated Al anode. The thicknesses of the Ag-doped IPS and IPS nanosheets were measured by atomic force microscope (Bruker). UV-visible absorption spectra were measured by the MStarter ABS deep UV-near infrared micro-absorption spectroscopy test system.

Calculation method

All first-principles calculations were performed within the Vienna Ab Initio Simulation Package (VASP) based on DFT (34). The projector augmented wave (PAW) potentials are used to deal with the electronic exchange-correlation interaction along with the GGA functional in the parameterization of the Perdew, Burke, and Ernzerhof (PBE) pseudopotential (35, 36). A plane wave representation for the wave function with a cutoff energy of 450 eV is applied. Geometry optimizations are performed using a conjugate gradient minimization until all the forces acting on the ions are less than 0.01 eV/Å per atom. In the calculations, the 2 × 2 × 2 k-point mesh is adopted (37). The climbing image nudged elastic band (CI-NEB) method is adopted to calculate diffusion barriers of Ag in In_4/3P₂S₆ and Ag-doped In_4/3P₂S₆ (38, 39). The DFT-D3 method is used to describe the van der Waals interaction (40). The formation energies of Ag occupying different vacancies are calculated by the following formula:

$$E_{\text{formation}}=E_{\text{occupied}}-E_{\text{pure}}-{\mathrm{\mu }}_{\text{Ag}}+{\mathrm{\mu }}_{\text{occupied}}$$

where E_occupied and E_pure are the total energies of Ag-doped In_4/3P₂S₆ and pure In_4/3P₂S₆, respectively. μ_Ag or μ_occupied is the corresponding chemical potential of Ag, S, or P atoms.

Supplementary Materials

This PDF file includes:

Notes S1 to S4

Figs. S1 to S28

Tables S1 and S2

References